SAR ADC Capacitor Array Reassembly for Fast Low-Power Conversion
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Solution Overview
Problem
Traditional binary SAR ADCs face challenges in achieving high-speed and low-power analog-to-digital conversion due to large capacitance mismatch and high power consumption, especially when increasing precision, which limits speed and precision and results in high economic costs.
Innovation Solution
A high-speed and low-power SAR ADC is developed, incorporating a sample and hold circuit, a binarization circuit with a DAC capacitor array using binary redundancy reassembly, and a digital error correction circuit, which reduces the number of unit capacitors and introduces redundancy to improve quantization speed and precision without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional binary SAR architecture is used to implement high-precision ADC, then precision is improved, but power consumption increases and conversion rate decreases
Solution Approach 1:
The capacitor array is divided into multiple segments with different capacitance weights. Instead of using a complete binary array for all precision bits, the array is segmented such that higher-order bits use larger capacitors and lower-order bits use smaller capacitors, reducing the total capacitance sum while maintaining precision requirements.
Solution Approach 2:
Different segments of the capacitor array are assigned different capacitance values based on their position in the binary weight hierarchy. This local differentiation allows the system to achieve high precision where needed while minimizing total capacitance in less critical regions, thereby reducing power consumption and improving conversion rate.
2Measurement precision
If the number of precision bits is increased, then measurement precision is improved, but the total capacitance of the DAC capacitor array increases exponentially
Solution Approach 1:
The capacitor array is segmented into multiple groups where each group handles a specific range of precision bits. By segmenting the array, the total capacitance grows linearly with the number of segments rather than exponentially with the total number of precision bits, as each segment can be optimized independently.
Solution Approach 2:
The patent introduces a new dimension of organization by grouping capacitors into segments with different weight factors. This dimensional reorganization transforms the capacitance scaling from exponential (2^N) to a more manageable growth rate, allowing high precision bits to be achieved without proportional exponential increase in total capacitance.
3Measurement precision
If a large quantity of unit capacitors are used to improve precision, then measurement precision is improved, but chip area increases
Solution Approach 1:
The capacitor array is divided into segments that can be arranged more compactly on the chip. By segmenting the array and using non-uniform capacitance distribution, the physical layout can be optimized to reduce the total area occupied while maintaining the required precision through the segmented structure.
Solution Approach 2:
Different regions of the chip are allocated different capacitor densities based on precision requirements. High-precision segments are placed in areas where area can be efficiently utilized, while lower-precision segments use less area, optimizing the overall chip area utilization and reducing total area consumption.
4Measurement precision
If the capacitance of unit capacitor is increased to reduce parasitic capacitor proportion, then measurement precision is improved, but power consumption increases
Solution Approach 1:
Instead of increasing the capacitance of all unit capacitors uniformly, the patent segments the array and increases capacitance only in segments where precision is most critical. This selective capacitance enhancement reduces the overall power consumption compared to uniformly increasing all capacitor values, while still achieving the required precision in critical segments.
Solution Approach 2:
The capacitance values are locally optimized in different segments based on precision requirements. Segments handling critical precision bits have larger capacitance values to minimize parasitic effects, while segments handling less critical bits use smaller capacitance values, thereby reducing total power consumption while maintaining overall precision.
Data Source
AI summary
The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.