SAR ADC Capacitor Sampling for Gain and Noise Suppression
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Solution Overview
Problem
Existing SAR ADCs face challenges in amplifying input signal amplitude while minimizing noise and capacitor size, as the size of the sampling capacitor is inversely proportional to the square of the signal amplitude, and traditional programmable gain amplifiers contribute additional noise and area occupancy.
Innovation Solution
The SAR ADC employs a novel configuration where both top and bottom plates of capacitors are used for sampling, allowing simultaneous amplitude amplification, reducing the required sampling capacitor size, and converting pseudo-differential signals to full differential signals to suppress noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a programmable gain amplifier (PGA) is used to amplify the input signal amplitude, then the signal amplitude is increased, but the chip area increases and additional noise is introduced
Solution Approach 1:
The patent combines the signal amplification function with the existing capacitor array structure by utilizing both top and bottom plates of capacitors for sampling. This integration eliminates the need for a separate PGA module, thereby avoiding additional chip area occupation while achieving signal amplification through the capacitive structure itself.
Solution Approach 2:
The capacitor array is designed to perform multiple functions: it serves as both the sampling capacitor and the signal amplification mechanism. By configuring both top and bottom plates to participate in sampling, the structure achieves programmable gain without requiring dedicated amplification hardware, thus reducing overall chip area while maintaining amplification capability.
2Illumination intensity
If a programmable gain amplifier (PGA) is used to amplify the input signal amplitude, then the signal amplitude is increased, but additional noise is contributed
Solution Approach 1:
The patent merges the amplification function into the passive capacitor structure, eliminating the active PGA component that introduces noise. The signal amplification is achieved through the capacitive voltage division and switching mechanism, which are passive operations that do not add thermal or flicker noise associated with active amplifiers.
Solution Approach 2:
The patent converts the inherent capacitive noise (kT/C noise) into a beneficial mechanism by using the capacitor switching and configuration to achieve amplification. Instead of trying to eliminate all noise sources, the design accepts and works with the fundamental capacitive noise while avoiding additional noise from active amplifiers, thereby achieving net noise reduction.
3Area of stationary object
If the amplitude of the input signal is increased, then the size of the sampling capacitor can be reduced, but traditional amplification methods increase chip area
Solution Approach 1:
The patent implements dynamic signal amplification through programmable capacitor switching and configuration. By dynamically reconfiguring which capacitors are connected to the input signal during different phases, the system achieves variable gain that effectively amplifies the signal amplitude, allowing for smaller capacitor sizes while maintaining adequate signal levels for conversion.
Solution Approach 2:
The patent transitions from single-plate to dual-plate capacitor utilization, adding a dimensional aspect to the sampling process. By engaging both top and bottom plates in the sampling operation with different weighting factors, the system creates an effective signal amplification mechanism that reduces the required physical capacitor size while achieving the necessary signal amplitude for accurate ADC conversion.
Data Source
AI summary
Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.