SAR ADC Capacitor Segmentation for Faster Small-Signal Conversion
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face performance degradation when dealing with small input signals, as they require a reference voltage higher than the input signal, leading to increased rise times and reduced logic circuit speed, and existing solutions either impact area and power considerations or introduce errors through signal amplification.
Innovation Solution
Configuring the most-significant bit (MSB) capacitor of the internal DAC to take input from the supply voltage VDD instead of the reference voltage VREF, allowing for faster voltage development and simplifying the VREF design, while also driving more significant bits with VDD to enhance speed and reduce capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage VREF is set higher than the input signal to ensure proper ADC operation, then the ADC can process small input signals, but the rise time increases and logic circuit speed decreases
Solution Approach 1:
The capacitor bank is segmented into two groups: capacitors associated with more significant bits (MSB group) and capacitors associated with less significant bits (LSB group). The MSB group is driven by the supply voltage VDD while the LSB group is driven by the reference voltage VREF. This segmentation allows different voltage sources to be used for different bit groups, resolving the contradiction between reliable operation and fast speed.
Solution Approach 2:
Different voltage driving conditions are applied to different parts of the capacitor bank based on their significance. The MSB capacitors use VDD for faster switching, while the LSB capacitors use VREF for precise voltage reference. This local differentiation optimizes both speed and accuracy in their respective domains.
2Reliability
If signal amplification is used to handle small input signals, then the ADC can process small signals, but errors are introduced through the amplification process
Solution Approach 1:
The capacitor bank is segmented into two groups: capacitors associated with more significant bits (MSB group) and capacitors associated with less significant bits (LSB group). The MSB group is driven by the supply voltage VDD while the LSB group is driven by the reference voltage VREF. This segmentation allows different voltage sources to be used for different bit groups, resolving the contradiction between reliable operation and fast speed.
Solution Approach 2:
Different voltage driving conditions are applied to different parts of the capacitor bank based on their significance. The MSB capacitors use VDD for faster switching, while the LSB capacitors use VREF for precise voltage reference. This local differentiation optimizes both speed and accuracy in their respective domains.
3Area of stationary object
If the capacitor size is reduced to decrease area, then the ADC area is reduced, but the decoupling capacitor requirements increase
Solution Approach 1:
The capacitor bank is segmented into two groups: capacitors associated with more significant bits (MSB group) and capacitors associated with less significant bits (LSB group). The MSB group is driven by the supply voltage VDD while the LSB group is driven by the reference voltage VREF. This segmentation allows different voltage sources to be used for different bit groups, resolving the contradiction between reliable operation and fast speed.
Solution Approach 2:
Different voltage driving conditions are applied to different parts of the capacitor bank based on their significance. The MSB capacitors use VDD for faster switching, while the LSB capacitors use VREF for precise voltage reference. This local differentiation optimizes both speed and accuracy in their respective domains.
Data Source
AI summary
An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=M*VDD, where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=M*VDD, where M<1, wherein the first capacitor having a capacitive value that is equal to (1−M)times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (VIN) signal as the second input to the comparator.