SAR ADC Capacitor Array Sequencing for Charge Retention
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Solution Overview
Problem
Analog-to-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face challenges in minimizing charge loss in capacitor arrays when switching phases due to timing errors, leading to inaccuracies in digital data conversion.
Innovation Solution
The implementation of a control logic circuit that controls the switching sequence of switches applying common mode voltage and reference voltages to a capacitor array, ensuring sequential and timed switching from minimum to maximum capacitance, thereby preventing charge loss during phase transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switches connected to capacitors are turned on simultaneously during phase switching, then the switching operation is simple, but timing errors cause charge loss through the common switch
Solution Approach 1:
The patent applies preliminary action by turning on switches connected to capacitors with larger capacitance values before switching the common switch, and turning on switches connected to capacitors with smaller capacitance values after switching the common switch. This pre-planned sequential switching sequence prevents charge loss by ensuring that capacitors contributing most to the total capacitance are already connected before the common switch changes state, thereby maintaining charge retention accuracy without requiring complex real-time coordination
2Measurement precision
If sequential switching from minimum to maximum capacitance is implemented, then charge loss is minimized, but the switching sequence control becomes more complex
Solution Approach 1:
The patent applies parameter changes by utilizing the capacitance value parameter of each capacitor to determine the switching sequence. Switches are controlled in a specific order based on their associated capacitor's capacitance value - larger capacitance switches are activated before the common switch, while smaller capacitance switches are activated after. This parameter-based sequencing strategy achieves accurate digital data conversion by minimizing charge loss, while the control complexity is managed through a systematic approach that leverages existing capacitor characteristics
Data Source
AI summary
The present disclosure relates to an analog-to-digital converter that minimizes or prevents a loss of charges charged in a capacitor array by controlling a switching sequence of switches when switching phases. The analog-to-digital converter includes a DAC circuit including a CDAC circuit and a RDAC circuit, a comparator that compares an output voltage of the DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the DAC circuit and the comparison operation of the comparator in a sampling phase and a comparison phase, outputs digital data based on the comparison result of the comparator, and controls switches that apply the common mode voltage and first and second reference voltages to the capacitor array in the CDAC circuit in response to that the sampling phase is switched to the comparison phase based on a specific switching timing sequence.