SAR ADC Capacitor Shuffling for SNR and Linearity Gain
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Solution Overview
Problem
Existing SAR ADCs face errors due to noise and capacitor mismatch during analog to digital conversion, which degrades the linearity of the digital output.
Innovation Solution
The implementation of incremental delta modulation (IDM) and dynamic element matching (DEM) in SAR ADCs, where capacitors are grouped into segmented sets and shuffled for each cycle, followed by averaging the outputs to compensate for errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional SAR ADC with binary weighted capacitors is used, then conversion speed is maintained, but noise and capacitor mismatch degrade linearity and accuracy
Solution Approach 1:
The capacitor array is divided into multiple segmented sets (e.g., first set, second set, third set) with each set containing capacitors of equal capacitance. This segmentation allows dynamic selection and shuffling of capacitors across different sets during conversion cycles, reducing the impact of individual capacitor mismatches and noise on overall conversion accuracy.
Solution Approach 2:
The patent implements dynamic element matching (DEM) where capacitors are shuffled and reassigned to different weight positions in each conversion cycle. This dynamic reconfiguration ensures that systematic errors from capacitor mismatch are averaged out over multiple cycles, improving linearity without sacrificing conversion speed.
2Measurement precision
If capacitor shuffling and averaging is implemented, then noise and mismatch errors are reduced, but device complexity increases
Solution Approach 1:
By organizing capacitors into segmented sets with identical capacitance values, the patent simplifies the shuffling process compared to traditional binary-weighted arrays. Each set can be independently controlled and switched, reducing the complexity of individual capacitor management while achieving error reduction through averaging across sets.
Solution Approach 2:
Multiple sets of capacitors are created as copies of each other (each set containing capacitors of equal capacitance). These duplicate sets allow the system to perform multiple conversions with different capacitor assignments and average the results, reducing noise and mismatch errors without requiring complex individual capacitor adjustments.
3Measurement precision
If incremental delta modulation with multiple cycles is used, then resolution is enhanced, but conversion time increases
Solution Approach 1:
The patent performs multiple conversion cycles with periodic capacitor shuffling and averaging. By structuring the conversion process into discrete, repeating cycles where capacitors are systematically reassigned and results are averaged, the patent achieves higher resolution through multiple measurements while maintaining a predictable and efficient conversion timeline.
Solution Approach 2:
Capacitors are pre-organized into segmented sets with defined relationships before conversion begins. This preliminary structuring allows rapid shuffling and reassignment during each cycle without requiring complex real-time calculations, enabling multiple conversion cycles to be completed efficiently with reduced overall conversion time.
Data Source
AI summary
A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.