SAR ADC Capacitor Switching to Reduce Code-Dependent Errors
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Solution Overview
Problem
Conventional SAR ADCs face errors due to disturbances in reference voltages and impedance mismatch between PMOS and NMOS switches, leading to poor signal-to-noise ratio and distortion.
Innovation Solution
The SAR ADC employs a switch-capacitor DAC with a control circuit that predicts digital code bits and adjusts capacitor terminal voltages in the sampling phase, reducing impedance mismatch and error dependency on digital code output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional switch-capacitor DAC with PMOS and NMOS switches is used, then the SAR ADC can be implemented with standard circuit structures, but impedance mismatch between PMOS and NMOS causes errors and poor signal-to-noise ratio
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary between the switch-capacitor DAC and the comparator. This buffer circuit acts as a mediator that isolates the impedance mismatch effects of PMOS and NMOS switches from the comparator input, thereby improving signal-to-noise ratio while maintaining the use of standard circuit structures.
Solution Approach 2:
The patent segments the DAC structure into multiple capacitor arrays (first capacitor array and second capacitor array) with separate switch groups. This segmentation allows independent optimization of each segment and reduces the overall impact of impedance mismatch by distributing the switching operations across multiple smaller units.
2Device complexity
If reference voltage disturbances occur during comparison and switching operation, then the SAR ADC can operate with simple voltage references, but errors are introduced at the comparator input terminals
Solution Approach 1:
The patent employs capacitive coupling to establish equipotential relationships between corresponding nodes in the first and second capacitor arrays. By maintaining equal potential differences across coupled capacitors during switching operations, the circuit minimizes the impact of reference voltage disturbances on the comparator input terminals.
Solution Approach 2:
The patent implements a feedback mechanism where the comparator output is fed back to the SAR logic, which then adjusts the switching states of the capacitor arrays. This feedback loop continuously compensates for errors introduced by reference voltage disturbances, maintaining high measurement precision.
3Productivity
If capacitor terminal voltages are switched according to digital code during comparison phase, then the SAR ADC can perform successive approximation, but errors increase due to dependency on digital code output
Solution Approach 1:
The patent performs preliminary switching of capacitor terminal voltages during the sampling phase, before the comparison phase begins. By pre-establishing the correct voltage states on the capacitor bottom plates based on the input signal, the circuit reduces the magnitude of subsequent switching operations during comparison, thereby minimizing errors while maintaining fast conversion speed.
Data Source
AI summary
A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.