SAR ADC CDAC Calibration for Capacitor Mismatch Correction
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Solution Overview
Problem
Successive approximation ADCs with capacitor-based digital-to-analog converters (CDACs) face inaccuracies due to capacitor mismatch, leading to distortion in digital output, which is difficult to correct without increasing capacitor size and power consumption.
Innovation Solution
A calibration method that measures and corrects static capacitor mismatches using a look-up table at the output of the successive approximation register logic, allowing for higher matching accuracy with smaller capacitors, thereby reducing silicon area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the size of integrated capacitors is increased to improve matching accuracy, then capacitor matching precision is improved, but chip area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before normal ADC operation. The calibration process pre-determines correction values for capacitor mismatches and stores them in lookup tables, so that during normal operation, the ADC can use these pre-computed corrections without needing larger capacitors. This resolves the contradiction by achieving high matching accuracy through pre-calibration rather than through physically larger capacitors.
Solution Approach 2:
The patent changes the operational parameters of the ADC by introducing calibration modes with specific switch configurations and measurement sequences. By varying the calibration parameters (switch positions, measurement timing, reference voltage selections) and storing the results in lookup tables, the system achieves high capacitor matching accuracy without requiring physically larger capacitors, thus reducing chip area while maintaining precision.
2Manufacturing precision
If the size of integrated capacitors is increased to improve matching accuracy, then capacitor matching precision is improved, but power consumption increases
Solution Approach 1:
The calibration process performs all energy-intensive matching measurements in advance before normal operation. The lookup tables store pre-computed correction values, eliminating the need for continuous high-power operation during normal ADC conversion. This resolves the power consumption contradiction by front-loading the energy expenditure into a brief calibration phase rather than requiring sustained high power for capacitor drivers.
Solution Approach 2:
The patent uses small, inexpensive capacitors that would normally be insufficient for high-precision applications, but compensates by using a one-time calibration process with lookup table corrections. The calibration phase consumes energy to characterize the actual capacitor values, but during normal operation, the system achieves high accuracy without needing large, power-hungry capacitors. This trades a brief calibration energy expense for reduced ongoing power consumption.
3Productivity
If capacitor-based digital-to-analog converters are used in successive approximation ADCs, then conversion functionality is achieved, but distortion occurs due to capacitor mismatch
Solution Approach 1:
The patent implements feedback by measuring the actual capacitor values during calibration, computing correction values based on these measurements, and applying corrections through lookup tables during normal operation. The system continuously monitors and corrects for capacitor mismatches, ensuring high output accuracy while maintaining fast conversion capability. This feedback mechanism resolves the contradiction between productivity and reliability.
Solution Approach 2:
The patent replaces the mechanical/physical solution of using larger capacitors to achieve better matching with a digital/computational solution. Instead of physically enlarging capacitors to reduce mismatch, the system uses digital calibration measurements, lookup tables, and correction algorithms to compensate for capacitor variations. This substitution maintains fast ADC conversion while achieving high accuracy through digital processing rather than analog component scaling.
Data Source
AI summary
A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.