SAR ADC CDAC Calibration for Linearity Without Larger Capacitors
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Solution Overview
Problem
The challenge in achieving high linearity in successive approximation register analog-to-digital converters (SAR ADCs) is exacerbated by mismatched parameters of elements during the manufacturing process, particularly affecting the capacitor digital-to-analog converter (CDAC), which requires a calibration method to reduce unit capacitance and improve overall performance without increasing dynamic power consumption.
Innovation Solution
A calibration method for SAR ADCs that involves coupling capacitors to reference voltages and generating digital codes to calculate capacitor weights, allowing for precise calibration of the ADC without adding additional circuits, thereby reducing element size and dynamic power consumption while improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the unit capacitance of the CDAC is increased to achieve better linearity, then the manufacturing precision improves, but the device area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before the actual ADC conversion. The calibration process pre-determines the capacitor weights by comparing digital codes generated with different capacitor configurations, allowing the system to compensate for manufacturing variations without requiring larger capacitors during normal operation.
Solution Approach 2:
The patent changes parameters by dynamically adjusting which capacitors are connected to reference voltages during calibration. By varying the connection states of capacitors to different reference voltages and measuring the resulting digital codes, the system determines actual capacitor weights and uses this information to correct for mismatches, achieving high linearity without increasing physical capacitor size.
2Manufacturing precision
If the unit capacitance of the CDAC is increased to achieve better linearity, then the manufacturing precision improves, but the power consumption increases
Solution Approach 1:
The calibration is performed in advance to determine capacitor weights before actual conversion operations. This preliminary characterization allows the system to use smaller capacitors during normal operation while maintaining high linearity through digital correction based on the pre-measured weights, thereby reducing dynamic power consumption.
Solution Approach 2:
The patent replaces physical capacitor size adjustments with digital processing. Instead of using larger capacitors to achieve better matching, the system measures actual capacitor weights and applies digital correction algorithms, substituting mechanical/physical solutions with electronic/computational ones that consume less power.
3Manufacturing precision
If additional calibration circuits are added to improve linearity, then the manufacturing precision improves, but the device complexity increases
Solution Approach 1:
The patent makes the existing ADC circuits multi-functional by using them for both calibration and normal conversion operations. The same CDAC, comparator, and control logic are reused in calibration mode, eliminating the need for separate dedicated calibration hardware and reducing overall device complexity.
Solution Approach 2:
The ADC system performs its own calibration using its existing components. The calibration process utilizes the CDAC, comparator, and control logic already present in the ADC, allowing the system to self-characterize and self-correct without requiring external calibration equipment or additional dedicated calibration circuits.
Data Source
AI summary
A successive approximation register analog-to-digital converter (SAR ADC) with calibration function and a calibration method thereof are provided. The SAR ADC has at least one capacitor digital-to-analog converter (CDAC), having Nd capacitors corresponding to Nd bits; and a controller. The calibration method includes: coupling the capacitors of an i-th to an (Nd−1)-th bit to a first reference voltage, and generating a first digital code based an operation of the capacitors of an (i−1)-th bit to a 0-th bit; coupling the capacitors of an (i+1)-th bit to the (Nd−1)-th bit to the first reference voltage, coupling the capacitor of the i-th bit to a second reference voltage, and generating a second digital code based on the operation of the capacitors of the (i−1)-th bit to the 0-th bit; generating a capacitor weight of the capacitor of the i-th bit; and calibrating the SAR ADC based on the capacitor weight.