SAR ADC CDAC Control Circuit Setup Time Reduction
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Solution Overview
Problem
The time required for decision feedback to a capacitive digital-to-analog converter (CDAC) in successive approximation register (SAR) analog-to-digital converters (ADCs) limits the conversion rate, as it is constrained by the time needed for digital circuitry to generate control signals for reference voltage switches, which includes setup time delays in flip-flops.
Innovation Solution
The implementation of a CDAC control circuit that eliminates flip-flop setup time delays by using a constant voltage source for data input terminals and optimizing clock signals, thereby reducing the time needed to generate control signals for next bit comparisons, and improving conversion accuracy by reducing overall conversion time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional flip-flop based control circuitry is used to generate control signals for CDAC, then the circuit design is straightforward and reliable, but the setup time delays increase the total conversion time and limit the conversion rate
Solution Approach 1:
The patent extracts and eliminates the flip-flop component from the control circuitry, replacing it with a direct logic circuit implementation. This removal of the flip-flop eliminates the associated setup time delay while maintaining the essential control signal generation function, directly resolving the time delay problem without compromising circuit reliability
Solution Approach 2:
The patent changes the temporal parameter of control signal generation by transitioning from a sequential flip-flop-based timing mechanism to a combinatorial logic-based instantaneous generation. This parameter change in the timing mechanism eliminates the setup time delay, enabling faster conversion rates while maintaining proper signal sequencing through optimized logic design
2Measurement precision
If more iterations are performed to improve conversion accuracy, then the resolution increases, but the total conversion time increases proportionally
Solution Approach 1:
The patent implements preliminary action by pre-calculating and preparing control signals through optimized logic circuits before they are needed. The control signals are generated in advance through combinatorial logic rather than being sequentially produced, allowing the conversion process to proceed faster while maintaining the necessary number of iterations for accurate conversion
Solution Approach 2:
The patent ensures continuity of useful action by eliminating the idle setup time periods between control signal generations. The optimized control circuitry continuously generates control signals without the interruptions caused by flip-flop setup delays, maintaining maximum productivity throughout the conversion process while completing the required iterations for accurate conversion
Data Source
AI summary
An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.