SAR ADC CDAC Self-Calibration for Mismatch Error Correction
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Solution Overview
Problem
Existing SAR ADCs face challenges in achieving high resolution while maintaining small die size, due to issues with capacitor mismatch errors, signal attenuation, and temperature-dependent accuracy, which are exacerbated by methods like laser trimming and analog calibration that are costly and environmentally dependent.
Innovation Solution
A SAR ADC with a binary-weighted charge redistribution DAC using a self-calibration algorithm, where the calibration process is divided into error detection and correction, utilizing two sets of capacitor arrays to provide error correction signals and compensate for mismatch errors, allowing for continuous correction and maintaining accuracy across temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser trimming is used to improve capacitor mismatch accuracy, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements self-calibration functionality within the SAR ADC system, where the ADC automatically detects and corrects its own capacitor mismatch errors through built-in calibration circuits and algorithms, eliminating the need for external laser trimming processes and achieving continuous self-correction of accuracy degradation
Solution Approach 2:
The patent performs calibration measurements and stores correction coefficients in lookup tables before normal conversion operations, allowing the system to pre-compute and store error correction data that can be quickly applied during operation without real-time complex calculations
2Manufacturing precision
If analog calibration is performed to improve ADC accuracy, then manufacturing precision is improved, but production time and cost increase
Solution Approach 1:
The system performs self-calibration automatically without requiring external analog signal sources or manual intervention, using built-in test modes and internal signal generation to complete calibration procedures, significantly reducing production testing time and complexity
Solution Approach 2:
The patent performs calibration measurements and stores correction coefficients in lookup tables before normal conversion operations, allowing the system to pre-compute and store error correction data that can be quickly applied during operation without real-time complex calculations
3Manufacturing precision
If calibration capacitor array is added to correct mismatch errors, then ADC accuracy is improved, but die size increases
Solution Approach 1:
The patent combines the calibration capacitor array with the functional capacitor array of the DAC, allowing the same capacitor structures to serve both conversion and calibration purposes, thereby correcting mismatch errors without proportionally increasing die area
Solution Approach 2:
The patent divides the capacitor array into segments that can be selectively connected for calibration or normal operation, allowing error correction functionality to be integrated without requiring a completely separate calibration structure
4Manufacturing precision
If one-time calibration is performed at manufacture, then initial accuracy is improved, but temperature stability deteriorates
Solution Approach 1:
The system performs automatic self-calibration at power-up and can re-calibrate during operation to compensate for temperature drift and aging effects, maintaining accuracy over time and temperature variations without requiring manual re-calibration
Solution Approach 2:
The patent implements feedback mechanisms where calibration coefficients are measured, stored in lookup tables, and applied during normal operation to continuously compensate for drift, ensuring long-term stability and accuracy maintenance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-resolution analog-to-digital conversion with reduced die size, improved signal integrity, and enhanced temperature stability by continuously correcting capacitor mismatch errors, thereby improving the signal-to-noise ratio and effective number of bits.
Implementation Method 1
a binary-weighted charge redistribution DAC
Data Source
AI summary
A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.