SAR ADC Reference Voltage Scheme for Lower CDAC Power
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Solution Overview
Problem
Conventional SAR ADCs use reference voltages equal to the maximum input voltage, which significantly affects the power consumption of the capacitive digital to analog converter (CDAC), and existing solutions do not effectively address comparator-hysteresis effects and power efficiency.
Innovation Solution
The SAR ADC employs a reference voltage that is about half the difference between the maximum and minimum input voltage, using a CDAC with a switch array of capacitors and a comparator to determine the most significant bit and subsequent bits, optimizing power usage and reducing comparator errors through a linear or binary search method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage is set equal to the maximum input voltage, then the ADC can cover the full input voltage range, but the power consumption of the CDAC increases significantly
Solution Approach 1:
The patent changes the reference voltage parameter from the conventional maximum input voltage to approximately half the peak-to-peak input voltage. This parameter change allows the CDAC to operate with lower voltage swings while still accurately representing the input signal through differential encoding, thereby reducing power consumption while maintaining full input range coverage
Solution Approach 2:
The patent introduces a differential encoding mechanism as an intermediary between the input voltage and the CDAC. By encoding the input voltage as a differential signal relative to a mid-range reference voltage, the system can represent the full input range without requiring the reference voltage to span the entire range, thus reducing CDAC power consumption
2Measurement precision
If a higher reference voltage is used in the CDAC, then the voltage resolution may be improved, but the power consumption increases
Solution Approach 1:
The patent optimizes the reference voltage parameter to approximately half the peak-to-peak input voltage, which provides sufficient voltage resolution for accurate ADC operation while significantly reducing the voltage swing amplitude. This reduced amplitude directly lowers the power consumption of the CDAC capacitors without sacrificing measurement precision, as the differential encoding maintains the necessary resolution
3Use of energy by moving object
If the reference voltage is reduced to save power, then the power consumption decreases, but the ability to accurately represent the full input range is compromised
Solution Approach 1:
The patent introduces differential encoding as an intermediary mechanism that allows a reduced reference voltage to still represent the full input range. By encoding the input voltage as a differential signal relative to the lower reference voltage, the system maintains accurate representation of the full input range while operating with lower voltage swings that reduce power consumption
4Device complexity
If conventional reference voltage levels are used, then the ADC design is simpler, but comparator-hysteresis effects and power efficiency are not effectively addressed
Solution Approach 1:
The patent changes the reference voltage parameter to approximately half the peak-to-peak input voltage and modifies the comparison operation to use differential encoding. This parameter change reduces comparator-hysteresis effects by operating in a more optimal voltage range while maintaining design simplicity through the systematic application of the differential encoding approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and improves the accuracy of the SAR ADC by efficiently determining the digital output word based on the comparison with the reference voltage, effectively addressing the limitations of conventional SAR ADCs in power usage and comparator performance.
Implementation Method 1
comparator 120 compares voltage Vcomp with reference voltage Vref and generates an output voltage corresponding with the results of the comparison
Implementation Method 2
conventional SAR ADC architectures use reference voltages which are equal to or are substantially equal to the maximum input voltage. Because the reference voltage is used in a capacitive digital to analog converter (CDAC)
Data Source
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Figure 2
Figure 3~4
AI summary
An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.