SAR ADC CDAC Switching to Cut Conversion Time
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Solution Overview
Problem
The existing analog-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face increased overall cycle time due to the need to reset comparators and set digital-to-analog converter (DAC) settings, which prolongs the analog-to-digital conversion process.
Innovation Solution
The proposed solution involves using multiple capacitor digital-to-analog converters (CDACs) that generate reference voltages before the comparator output is determined, allowing for faster operation by predetermining DAC settings and reducing the time required for analog-to-digital conversion through a switch circuit and logic circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple bits are determined with one comparator in SAR ADC, then device complexity is reduced, but conversion time increases due to sequential bit determination
Solution Approach 1:
The patent applies preliminary action by pre-calculating and preparing DAC setting values before the comparator output is generated. The logic circuit predicts the next bit value based on current comparison results and pre-sets the DAC accordingly, allowing the next comparison to start immediately without waiting for DAC settling time, thus reducing overall conversion time while maintaining single-comparator simplicity
Solution Approach 2:
The patent segments the conversion process into overlapping stages where the logic circuit continuously predicts next-bit values and pre-sets DAC settings in parallel with ongoing comparisons. This segmentation allows different operations (comparison, prediction, and DAC setting) to occur in overlapping time windows rather than strictly sequential phases, improving throughput without adding comparators
2Ease of operation
If CDAC setting is performed after comparator output is determined, then operation simplicity is maintained, but conversion speed is limited by sequential operation
Solution Approach 1:
The logic circuit performs preliminary action by predicting the next bit value and pre-setting the DAC before the current comparison cycle completes. This allows the DAC to be ready for the next comparison immediately, eliminating idle time and enabling faster operation while maintaining the simple single-comparator architecture
Solution Approach 2:
The patent implements continuity of useful action by ensuring the DAC is continuously active and preparing setting values in parallel with comparison operations. The logic circuit continuously updates predicted bit values, keeping the DAC in a state of continuous useful preparation rather than idle waiting, thus maximizing operational speed without complicating the system
Data Source
AI summary
An analog-to-digital converter (ADC) using a plurality of capacitor digital-to-analog converters (CDACs) includes a plurality of comparators, a plurality of CDACs each configured to generate a reference voltage, and a switch circuit configured to connect one CDAC among the plurality of CDACs to an n+1 comparator, based on a digital value output from an n comparator among the plurality of comparators, and the n+1 comparator may output a digital value based on a result of comparing the reference voltage of one CDAC among the plurality of CDACs with an input voltage.