SAR ADC Autozeroing for Switch Charge Injection Cancellation

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Solution Overview

Problem

SAR-ADCs face degradation in conversion results due to undesired charge injection from switches during the adjusting step, which is not fully compensated by the limited common mode rejection ratio (CMRR) of the comparator, especially with asymmetries in input nodes, capacitive loads, or switches.

Innovation Solution

The method involves closing switches to connect a capacitor to both the input voltage and mid voltage levels during sampling, then performing an autozeroing step after disconnecting the mid voltage, which includes sampling the error charge injected by the switches to completely cancel the offset, and optionally prolonging the autozeroing step to allow the comparator to settle and fully compensate for the parasitic charge injection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If switches are opened to disconnect mid voltage from capacitive array after sampling, then sampling phase is completed, but parasitic charge is injected into comparator input nodes causing offset voltage

Engineering Contradiction:
Improvesampling phase completionVSAvoidparasitic charge injection
Core Design Contradiction:
Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The autozeroing step is performed in advance before the actual conversion phase, capturing the offset voltage including parasitic charge effects on the comparator input nodes. This preliminary compensation ensures that when switches are later opened during conversion, the previously captured offset already accounts for any charge injection effects.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The parasitic charge injection, which is inherently harmful, is converted into a beneficial effect by including it in the offset voltage measurement during autozeroing. The comparator captures this harmful charge as part of the offset, and then subtracts it during conversion, effectively turning the harmful parasitic effect into a compensated parameter.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Object-affected harmful factors

If symmetric design is used for input nodes and capacitive loads, then common mode voltage is suppressed, but differential voltage errors occur due to unbalance and limited CMRR

Engineering Contradiction:
Improvecommon mode voltage suppressionVSAvoiddifferential voltage accuracy
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The comparator uses feedback through the autozeroing process to measure and compensate for differential voltage errors. By capturing the offset voltage that includes any differential errors caused by unbalance or limited CMRR, and then subtracting this offset during conversion, the system achieves high precision despite inherent asymmetries.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If autozeroing is performed before switches are opened, then offset is compensated, but parasitic charge injection is not fully canceled

Engineering Contradiction:
Improveoffset compensationVSAvoidcharge injection cancellation
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The autozeroing step is performed as a preliminary action that captures the complete offset voltage state, including any parasitic charges that will be present during conversion. This timing ensures that the offset measurement encompasses all harmful effects that will occur during the actual conversion phase.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2201688B1Method and device for controlling a successive approximation register analogue to digital converter
Publication Date: 2011.08.03 TEXAS INSTR DEUTLAND GMBH
  • EP2201688B1 patent drawingFigure 1
  • EP2201688B1 patent drawingFigure 2
  • EP2201688B1 patent drawingFigure 3

AI summary

A method for controlling a successive approximation register analogue to digital converter, comprises closing a first switch for connecting a capacitor with one side to a mid voltage level, the capacitor being coupled with the same side to a first comparator input, closing a second switch for connecting the capacitor with another side to an input having an input voltage level, opening the first switch, opening the second switch, and performing an autozeroing step with the comparator.