SAR ADC Reference Voltage Stabilization by Charge Compensation
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Solution Overview
Problem
In SAR type analog-to-digital converter circuits, the change in connection state of the capacitor array during resetting or comparison operations generates noise, causing variations in the reference voltage, which affects AD conversion accuracy.
Innovation Solution
The implementation of a charge compensation circuit that operates based on an internal operating voltage, compensating for charge at the reference voltage input node during AD conversion operations to stabilize the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bypass capacitor is provided inside the integrated circuit to inhibit self-noise and maintain AD conversion accuracy, then the reference voltage stability is improved, but the circuit area increases significantly
Solution Approach 1:
The patent segments the capacitor array into multiple sub-capacitor arrays, each connected to a separate switching unit. This segmentation allows independent control of charge distribution across different capacitor groups, enabling noise suppression without requiring a large bypass capacitor. The switching units can selectively connect or disconnect sub-capacitor arrays during reset and comparison operations, thereby controlling charge flow to minimize reference voltage fluctuations while occupying minimal circuit area.
Solution Approach 2:
The patent dynamically changes the connection state parameters of the capacitor array through control signals that switch capacitors between different configurations. By changing the connection states of switching units and capacitors at different operation stages (sampling, reset, comparison), the system optimizes charge distribution to suppress self-noise without requiring additional large-capacitance bypass capacitors, thus maintaining accuracy while minimizing area.
2Productivity
If the connection state of the capacitor array is changed during resetting or comparison operation, then the AD conversion operation can proceed, but noise is generated causing reference voltage to vary
Solution Approach 1:
The patent applies preliminary action by performing charge compensation before the comparison operation begins. The control unit activates switching units to connect sub-capacitor arrays to the reference voltage in advance, ensuring that charge is properly distributed and the reference voltage is stabilized before the comparison operation starts. This preliminary charge compensation prevents noise generation during the actual comparison, allowing normal AD conversion operation while eliminating self-noise.
Solution Approach 2:
The patent implements feedback control where the control unit monitors the operation stage (sampling, reset, comparison) and dynamically adjusts the connection states of switching units and capacitors accordingly. Based on feedback from the current operation phase, the control unit optimizes charge distribution in real-time, ensuring that capacitor array transitions occur in a manner that minimizes reference voltage fluctuations and self-noise generation while maintaining conversion productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively inhibits voltage variations in the reference voltage, thereby maintaining AD conversion accuracy without increasing the circuit area, even when external bypass capacitors are not feasible.
Implementation Method 1
a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, compensate the reference voltage input node for charge
Data Source
AI summary
An analog-to-digital converter circuit includes: a reference voltage node configured to be supplied with a reference voltage; an analog-to-digital converter circuit unit including a reference voltage input node configured to be electrically connected to the reference voltage node, the reference voltage being input to the reference voltage input node, the analog-to-digital converter circuit unit configured to convert an input analog voltage into a digital value based on the reference voltage; a voltage generation circuit configured to be electrically connected to the reference voltage node and generate an internal operating voltage based on the reference voltage; and a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, the charge compensation circuit configured to compensate the reference voltage input node for charge.