SAR ADC Charge Redistribution for Continuous Current Integration
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Solution Overview
Problem
Current analog-to-digital converters, such as SAR ADCs and Σ-Δ ADCs, face limitations in balancing resolution and conversion speed, with SAR ADCs having limited accuracy due to comparator noise and DAC errors, and Σ-Δ ADCs requiring high oversampling ratios that restrict conversion speed and SNR.
Innovation Solution
An analog-to-digital converter design that incorporates a capacitive digital-to-analog converter with a weight capacitor array and an auxiliary capacitor, performing residual charge storage, integration, and charge redistribution phases, along with an SAR conversion phase, to achieve continuous integration and improved signal-to-noise ratio, while using a digital filter and decimation circuit to average digital codes and enhance resolution and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SAR ADC is used for high-speed conversion, then conversion speed is improved, but measurement precision deteriorates due to comparator noise and DAC establishment error
Solution Approach 1:
The patent divides the conversion process into multiple sub-periods within one conversion frame, with each sub-period performing residual charge storage, integration, charge redistribution, and SAR conversion. This segmentation allows the system to accumulate integration results over multiple phases while maintaining high-speed SAR conversion capabilities, thereby improving both speed and precision simultaneously
Solution Approach 2:
The patent implements continuous integration across multiple sub-periods by storing residual charges from previous sub-periods and adding them to current integration results. This continuous accumulation of useful action over multiple phases improves measurement precision without sacrificing the high conversion speed of SAR ADC
2Measurement precision
If Σ-Δ ADC is used for high-resolution conversion, then measurement precision is improved, but conversion speed deteriorates due to high oversampling ratio requirements
Solution Approach 1:
The patent segments the conversion frame into multiple sub-periods, each performing complete integration and SAR conversion cycles. This segmentation allows the system to achieve high resolution through multiple integration phases while maintaining high conversion speed by processing results through fast SAR conversion in each sub-period, avoiding the speed limitations of traditional Σ-Δ ADC
Solution Approach 2:
The patent introduces a capacitive digital-to-analog converter and auxiliary capacitor as intermediary elements that enable continuous integration across sub-periods. These intermediaries allow the system to accumulate precision-improving integration effects while using SAR conversion mechanisms to maintain high speed, bridging the gap between Σ-Δ precision and SAR speed
3Measurement precision
If multiple sub-periods are used for continuous integration, then signal-to-noise ratio is improved, but device complexity increases
Solution Approach 1:
The patent designs the capacitive digital-to-analog converter and auxiliary capacitor to perform multiple functions across different sub-periods: storing residual charges, integrating input signals, and redistributing charges. This multi-functionality allows the same circuit elements to be reused across multiple sub-periods, improving signal-to-noise ratio through continuous integration while avoiding the need for separate dedicated circuits for each function, thereby controlling device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves time utilization and signal-to-noise ratio, eliminates quantization errors, and increases convergence rate, balancing resolution and conversion speed, while simplifying the engineering process and reducing circuit area and cost.
Implementation Method 1
an auxiliary capacitor, configured to store residual charge generated by the capacitive digital-to-analog converter in a previous sub-period at the residual charge storage phase, integrate an input current signal in addition to the weight capacitor array at the integration phase, and transfer the integration charge for the current sub-period to the weight capacitor array at the charge redistribution phase
Implementation Method 2
an amplifier that is coupled to the capacitive digital-to-analog converter and the auxiliary capacitor for performing charge transfer between the auxiliary capacitor and the weight capacitor array of the capacitive digital-to-analog converter
Implementation Method 3
a comparator that has an input being coupled to an output terminal of the amplifier, and is used for quantizing the output terminal of the amplifier to obtain a digital code
Data Source
AI summary
The present invention discloses an analog-to-digital converter and an operating method thereof. The analog-to-digital converter includes a plurality of sub-periods in one conversion frame, and performs at least the following operations in each sub-period: a residual charge storage phase, an integration phase, a charge redistribution phase, and an SAR conversion phase. The analog-to-digital converter includes a capacitive digital-to-analog converter and an auxiliary capacitor. The auxiliary capacitor stores residual charge generated by the capacitive digital-to-analog converter in a previous sub-period at the residual charge storage phase. A weight capacitor array of the capacitive digital-to-analog converter integrates an input current signal at the integration phase. The integration charge of the current sub-period is transferred to the weight capacitor array at the charge redistribution phase. It ensures that the analog-to-digital converter continuously integrates the input current signal in the entire conversion frame, improving time utilization and signal-to-noise ratio.