SAR ADC Capacitor Switching Sequence to Minimize Charge Loss
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Solution Overview
Problem
Analog-to-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, face charge loss issues in capacitor arrays due to switching timing errors when transitioning from the sampling phase to the comparison phase, leading to errors in digital code determination and inaccurate digital data output.
Innovation Solution
The implementation of a control logic circuit that controls the switching sequence of switches applying common mode voltage and reference voltages to the capacitor array, ensuring sequential switching based on specific timing sequences and switch types, thereby minimizing charge loss and preventing errors during phase transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switches are turned on simultaneously during phase transition, then switching speed is improved, but charge loss occurs due to timing errors
Solution Approach 1:
The patent applies preliminary action by turning on the first switch (connected to minimum capacitor) before turning off the common switch, and turning on the last switch (connected to maximum capacitor) after turning off the common switch. This sequential switching strategy ensures that charge paths are established before the common switch disconnects, preventing charge loss while maintaining efficient phase transition.
2Loss of energy
If sequential switching is used to prevent charge loss, then charge loss is minimized, but switching time increases
Solution Approach 1:
The patent applies partial action by implementing sequential switching only for the first and last switches in the array, while intermediate switches can be turned on simultaneously with the common switch turning off. This selective approach prevents charge loss at critical points (beginning and end of sequence) while minimizing the overall switching time penalty.
3Device complexity
If simultaneous switching is used, then device complexity is reduced, but measurement precision deteriorates due to charge loss
Solution Approach 1:
The patent applies segmentation by dividing the switch array into three groups: the first switch (minimum capacitor), intermediate switches, and the last switch (maximum capacitor). Different switching sequences are applied to each group, with the first and last switches requiring special timing to prevent charge loss, while intermediate switches follow standard simultaneous switching. This segmented approach maintains measurement precision while managing device complexity.
Data Source
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AI summary
The present disclosure relates to an analog-to-digital converter that minimizes or prevents a loss of charges charged in a capacitor array by controlling a switching sequence of switches when switching phases. The analog-to-digital converter includes a DAC circuit including a CDAC circuit and a RDAC circuit, a comparator that compares an output voltage of the DAC circuit with a common mode voltage and outputs a comparison result, and a control logic circuit that controls a switch operation of the DAC circuit and the comparison operation of the comparator in a sampling phase and a comparison phase, outputs digital data based on the comparison result of the comparator, and controls switches that apply the common mode voltage and first and second reference voltages to the capacitor array in the CDAC circuit in response to that the sampling phase is switched to the comparison phase based on a specific switching timing sequence.