SAR ADC Capacitor Array with Charge Transfer Sampling Precision
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Solution Overview
Problem
Conventional successive approximation register analog-to-digital converters (SAR ADCs) face issues of bandwidth mismatch due to multiple capacitors sampling at different rates and high noise requirements on the comparator, which degrade performance, especially at high input signal frequencies.
Innovation Solution
The introduction of a charge transfer capacitor and a redundant-bit capacitor array, along with a specific arrangement of weighted capacitors, allows for a single-capacitor sampling network, reducing noise requirements and eliminating bandwidth mismatch, thereby improving sampling precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple weighted capacitors perform sampling simultaneously in a conventional SAR ADC structure, then the chip area is reduced by not requiring additional sampling capacitors, but the sampling precision is degraded due to bandwidth mismatch caused by different parasitic resistors and capacitors on each capacitor sampling path
Solution Approach 1:
The patent divides the capacitor array into two separate arrays: a first capacitor array for sampling the first input signal and a second capacitor array for sampling the second input signal. This segmentation allows each capacitor array to have dedicated sampling paths with matched parasitic characteristics, eliminating bandwidth mismatch while maintaining compact chip area through the shared capacitor structure.
2Device complexity
If multiple weighted capacitors perform sampling simultaneously, then the structure remains simple, but the performance of the entire SAR ADC is directly degraded due to different voltages sampled by weighted capacitors
Solution Approach 1:
The patent segments the sampling function by dedicating the first capacitor array to sample the first input signal and the second capacitor array to sample the second input signal. This segmentation ensures that each signal has its own dedicated sampling path with matched parasitic characteristics, eliminating performance degradation while keeping the overall structure simple through the shared capacitor array design.
3Reliability
If the maximum amplitude of differential input signal is set to twice the supply-ground voltage difference of the comparator, then the reliability of the comparator is ensured, but the noise requirement on the comparator becomes excessively high
Solution Approach 1:
The patent introduces a voltage offset mechanism that acts as an intermediary between the differential input signal and the comparator. By adding a configurable offset voltage to the differential input signal before comparison, the system can operate with larger signal amplitudes while maintaining the comparator's reliable operating range, thereby reducing the noise requirement without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the signal-to-noise ratio and overall performance of the SAR ADC by allowing the comparator to handle higher input signal amplitudes without reliability loss, significantly improving sampling precision and reducing noise requirements.
Implementation Method 1
a capacitor array, including a first capacitor array and a second capacitor array, where the first capacitor array and the second capacitor array each include n−1 weighted capacitors and a charge transfer capacitor
Data Source
AI summary
A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n−1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n−2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and completing a jth time of comparison.