Successive Approximation ADC Clock Adaptation for Faster Conversion
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Solution Overview
Problem
Conventional successive approximation analog/digital converters operate with a constant conversion clock period, which is limited by the DAC setup time and comparator response time, leading to inefficiencies and time losses during the conversion phase, especially when the difference between the input voltage and the DAC output is small.
Innovation Solution
The conversion clock period is dynamically adapted based on measured parameters such as response times and setup times of the comparators and DAC, using a multiplexer, additional comparators, and an EXCLUSIVE-OR gate to generate an optimized clock signal, reducing the clock period while ensuring minimal clock width and noise insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a constant conversion clock period is used, then the conversion process is simple to implement, but time is lost during the conversion phase when the difference between input voltage and DAC output is small
Solution Approach 1:
The patent applies dynamics by making the conversion clock period variable rather than constant. The clock period is dynamically adjusted based on the absolute value of the difference between the input voltage and the DAC output voltage. When the difference is large, a longer clock period is used; when the difference is small, a shorter clock period is used, thereby reducing time loss during conversion while adapting to real-time conditions.
Solution Approach 2:
The patent changes the parameter of the conversion clock period from a fixed constant to a variable parameter that depends on the voltage difference. By measuring the absolute value of the difference between input voltage and DAC output and using this measurement to determine the clock period, the system optimizes conversion time based on actual operating conditions, reducing unnecessary time loss when the difference is small.
2Productivity
If the conversion clock period is reduced, then conversion speed improves, but the DAC setup time and comparator response time requirements become more stringent
Solution Approach 1:
The system dynamically adjusts the clock period based on the voltage difference magnitude. When the difference is large, there is sufficient time margin to accommodate DAC setup and comparator response requirements. When the difference is small, the system uses a shorter clock period only when the measured time loss would be significant, thereby maintaining reliability while improving overall conversion speed.
Solution Approach 2:
The patent implements feedback by measuring the absolute value of the difference between input voltage and DAC output, using this measurement to determine the appropriate clock period. This feedback mechanism ensures that the clock period is set appropriately based on actual circuit conditions, maintaining reliable operation while optimizing conversion speed.
3Productivity
If dynamic adaptation of conversion clock period is implemented, then conversion speed improves, but additional circuit components are required
Solution Approach 1:
The patent makes the existing conversion clock circuit multi-functional by adding a measurement mechanism that determines clock period based on voltage difference. The same clock generation circuit serves both constant and variable period operations, reducing the need for entirely separate circuitry and minimizing the increase in device complexity while achieving dynamic adaptation.
Solution Approach 2:
The system changes the operational parameter of the clock circuit from fixed to variable by incorporating voltage difference measurement. This allows the existing circuit infrastructure to be utilized more efficiently, achieving speed improvement without proportionally increasing the number of circuit components.
Data Source
AI summary
A successive approximation analog/digital converter is provided, which includes a successive approximation register supplying a digital/analog converter, first means of comparing an input signal of the analog/digital converter to an output signal of the digital/analog converter delivering a first comparison signal, said successive approximation analog/digital converter being synchronised by a clock signal coming from a conversion clock. A method such as this includes dynamic adaptation of the conversion clock period based on at least one parameter.