SAR ADC Comparator Clock Delay Calibration for High-Speed Accuracy
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face errors due to reference voltage settling issues at high speeds, and existing calibration techniques are computationally limited by resource constraints on integrated circuits.
Innovation Solution
A calibration method that applies a pattern of input signal values to adjust comparator clock delays based on error detection, using algorithms to iteratively adjust delays until errors fall below a threshold, thereby improving conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SAR ADC operates at very high speeds, then productivity is improved, but measurement precision deteriorates due to reference voltage settling errors
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before normal high-speed conversion. A calibration phase is executed first that measures and characterizes reference voltage settling behavior, storing correction data that is then applied during subsequent high-speed conversions. This allows the ADC to operate at high speeds while maintaining accuracy through pre-computed corrections.
Solution Approach 2:
The patent changes operational parameters by switching between calibration mode and conversion mode. During calibration, the ADC operates at lower speeds to accurately measure settling errors. During normal operation, it uses the stored calibration data to correct high-speed conversions. This parameter change allows optimization for both speed and accuracy at different times.
2Measurement precision
If complex calibration algorithms are implemented, then measurement precision is improved, but device complexity increases due to compute resource requirements
Solution Approach 1:
The patent applies self-service by having the ADC perform its own calibration using minimal external resources. The calibration algorithm uses the ADC's existing hardware components (DAC, comparator, control logic) to measure and correct its own errors, rather than requiring external calibration equipment or extensive additional circuitry. This reduces device complexity while maintaining precision improvement.
Solution Approach 2:
The patent uses copying by creating a simplified model of the conversion process during calibration. Instead of implementing complex real-time correction algorithms, the system measures settling errors during calibration and creates lookup tables or correction codes that are copied and applied during normal operation. This replaces complex computational requirements with simpler data storage and retrieval operations.
Data Source
AI summary
Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.