SAR ADC Clock Delay Calibration for Conversion Linearity
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Solution Overview
Problem
SAR ADC circuits with poor clock calibration or no calibration suffer from conversion linearity deterioration and increased power consumption due to inadequate clock timing.
Innovation Solution
A delay control circuit with parallel delay capacitors and inverters is used to create a delayed asynchronous clock, which is calibrated to determine the maximum delay value, ensuring sufficient settle time for bit capacitors and improving conversion linearity while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If no clock calibration is performed in SAR ADC circuit, then device complexity is reduced, but conversion linearity deteriorates and power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing clock calibration before the actual ADC conversion process. A delay control circuit is used to pre-adjust the timing of the asynchronous clock signal that controls the comparator, ensuring optimal settle time for the bit capacitors is achieved before conversion begins. This preliminary timing adjustment prevents conversion linearity deterioration without adding complex real-time calibration mechanisms during operation.
Solution Approach 2:
The patent changes the timing parameter of the comparator control clock by introducing a variable delay control circuit. This circuit adjusts the delay time of the asynchronous clock signal to optimize the settle time of bit capacitors. By dynamically adjusting the clock timing parameter rather than adding complex calibration hardware, the patent maintains conversion linearity while controlling device complexity.
2Device complexity
If no clock calibration is performed in SAR ADC circuit, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent performs clock timing optimization in advance using a delay control circuit that adjusts the asynchronous clock delay before conversion. By pre-configuring the optimal clock timing to ensure proper bit capacitor settling, the circuit avoids the need for continuous power-consuming calibration mechanisms during operation, thus reducing overall power consumption while maintaining simplicity.
Solution Approach 2:
The delay control circuit is configured to automatically adjust the clock timing parameters to optimize comparator operation and bit capacitor settling. This self-adjusting mechanism ensures proper timing without requiring external calibration hardware or continuous intervention, reducing power consumption while maintaining conversion accuracy.
3Measurement precision
If delayed asynchronous clock is used to extend settle time, then conversion linearity is improved, but device complexity increases
Solution Approach 1:
The patent introduces a delay control circuit as an intermediary component between the asynchronous clock source and the comparator. This intermediary circuit adjusts the clock timing to provide sufficient settle time for bit capacitors, improving conversion linearity. The delay control circuit is implemented using simple delay elements and control logic that work with the existing SAR ADC architecture, minimizing the increase in device complexity while achieving the desired timing optimization.
4Measurement precision
If clock timing is optimized for bit capacitor settling, then conversion accuracy is improved, but conversion speed may be reduced
Solution Approach 1:
The patent uses a dynamic delay control circuit that can adjust the clock timing parameters based on operational requirements. The circuit optimizes the settle time of bit capacitors by dynamically adjusting the asynchronous clock delay, ensuring accurate conversion without requiring excessive fixed delay. This dynamic adjustment allows the system to maintain high conversion accuracy while minimizing the impact on conversion speed by using the minimum necessary delay for proper settling.
Data Source
AI summary
An ADC circuit is provided. The ADC circuit may include an array of bit capacitors; a comparator electrically connected to the bit capacitors; a NOR gate electrically connected to the comparator; an AND gate to create an asynchronous clock (ACLK) based on a digital output from the NOR and a synchronous clock (CLKin); a delay control circuit to receive the asynchronous clock and to create a delayed asynchronous clock (ACLKd); and a SAR control circuit to receive a digital output from an output end of the comparator, to receive the delayed asynchronous clock, to transmit a bit control signal (B<9:1>) to the bit capacitors, and to transmit a delay control word (DL<7:1>) to the delay control circuit. The ADC circuit can create an asynchronous comparator clock (CKcmp) with a maximum delay value (Td_max), thus leading to an improved conversion linearity and a reduced power consumption.