SAR ADC Clock-Edge Comparison for Fast High-Resolution Output
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Solution Overview
Problem
Existing analog to digital converters using successive approximation methods face limitations in data processing speed, particularly in generating high-resolution digital outputs efficiently.
Innovation Solution
The proposed solution involves an analog to digital converter design that includes a digital to analog converting circuit, a comparator, and a signal processing circuit, which samples and holds an analog input signal, compares it with a reference voltage using both rising and falling edges of a clock signal, and performs successive approximation to generate digital output data, potentially utilizing dual comparators and preamplifiers to enhance resolution and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional successive approximation ADC design is used, then circuit complexity is reduced, but data processing speed is limited
Solution Approach 1:
The patent divides the comparison operation into two separate comparators: a first comparator that operates on the rising edge of the clock signal and a second comparator that operates on the falling edge. This segmentation allows parallel processing of comparison operations, thereby increasing data processing speed without requiring a single complex high-speed comparator
Solution Approach 2:
The patent utilizes both rising and falling edges of the clock signal for comparison operations, effectively doubling the utilization of the clock cycle. The first comparator operates during the rising edge period while the second comparator operates during the falling edge period, achieving faster conversion within the same clock frequency
2Measurement precision
If dual comparators and preamplifiers are added to enhance resolution and reduce noise, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces a preamplifier that operates during the sampling period to amplify the analog input signal before it reaches the comparators. This segmentation of the signal path allows the preamplifier to prepare the signal in advance, improving signal quality and measurement precision without requiring the comparators themselves to be overly complex
Solution Approach 2:
The preamplifier performs preliminary amplification of the analog input signal during the sampling period, before the comparison operation begins. This preliminary action ensures that the signal is properly conditioned and amplified in advance, improving measurement precision while keeping the comparison stage simpler
Data Source
AI summary
An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.