SAR ADC Clock Switching for Variable Resolution and Sampling Rate
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Solution Overview
Problem
Successive approximation analog-to-digital converters require high-speed control clocks for high sampling rates, leading to high power consumption, and existing asynchronous converters need wide variable delay circuits to adjust resolution and sampling rate, increasing circuit scale and power consumption.
Innovation Solution
A successive approximation analog-to-digital converter with capacitive elements, a comparator, registers, a DAC, and timing signal generation units that allow switching between synchronous and asynchronous modes to optimize clock selection and delay, preventing circuit scale enlargement while widening resolution and sampling rate variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a successive approximation ADC uses high-speed control clocks to achieve high sampling rates, then the sampling rate is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by providing multiple clock frequency options (first through fourth frequencies) that can be selected based on the required sampling rate. The system dynamically switches between synchronous and asynchronous operating modes, and adjusts clock frequencies to match the actual conversion requirements, avoiding unnecessary high-frequency operation and reducing power consumption while maintaining high sampling rate capability when needed.
Solution Approach 2:
The patent changes the operating parameters of the ADC by implementing variable conversion time and dual operating modes (synchronous and asynchronous). The system can switch between different conversion times (first and second conversion times) and operating modes based on the input signal characteristics and required output rate, allowing the sampling rate and power consumption parameters to be optimized for different operating conditions.
2Adaptability or versatility
If an asynchronous successive approximation ADC uses a wide variable delay circuit to adjust resolution and sampling rate over a wide range, then the adaptability is improved, but the circuit scale and power consumption increase
Solution Approach 1:
The patent segments the delay adjustment function into discrete, fixed delay stages rather than using a continuous wide variable delay circuit. By providing a plurality of fixed delay circuits with different delay amounts, the system achieves variable delay functionality through selective combination of discrete stages, reducing the complexity of implementing wide-range delay adjustment while maintaining adaptability for different resolutions and sampling rates.
Solution Approach 2:
The patent implements dynamic selection of delay amounts by providing multiple fixed delay circuits that can be selectively activated. The system dynamically chooses the appropriate delay stage based on the required conversion time and sampling rate, allowing flexible adaptation without requiring a complex continuously variable delay circuit. This dynamic switching between fixed delay stages achieves the desired variability with reduced circuit scale.
3Adaptability or versatility
If an asynchronous successive approximation ADC uses a wide variable delay circuit to adjust resolution and sampling rate over a wide range, then the adaptability is improved, but the power consumption increases
Solution Approach 1:
The patent segments the delay adjustment function into discrete, fixed delay stages rather than using a continuous wide variable delay circuit. By providing a plurality of fixed delay circuits with different delay amounts, the system achieves variable delay functionality through selective combination of discrete stages, reducing the complexity of implementing wide-range delay adjustment while maintaining adaptability for different resolutions and sampling rates.
Solution Approach 2:
The patent implements dynamic selection of delay amounts by providing multiple fixed delay circuits that can be selectively activated. The system dynamically chooses the appropriate delay stage based on the required conversion time and sampling rate, allowing flexible adaptation without requiring a complex continuously variable delay circuit. This dynamic switching between fixed delay stages achieves the desired variability with reduced circuit scale.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and circuit complexity by allowing flexible operation between synchronous and asynchronous modes, enabling efficient high-speed operation with adjustable resolution and sampling rates.
Implementation Method 1
a plurality of capacitive elements that sample an analog input signal and have weighted capacitance values
Implementation Method 2
a comparator that compares the analog input signal and a reference analog signal to output a comparison result
Implementation Method 3
a DAC that generates the reference analog signal based on the contents of the plurality of registers
Data Source
AI summary
The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.