SAR ADC Clocking With PLL Control to Minimize Linearity Errors
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Solution Overview
Problem
Successive approximation register analog to digital converters experience significant linearity errors due to leakage current from comparator input reset switches, especially at low sampling rates, strong CMOS model corners, and elevated temperatures when using deep submicron processes.
Innovation Solution
A clocking system with a phase locked loop and programmable counter is used to adjust the clock multiplier, reducing the duration of leakage current by sampling bits on N clock cycles instead of the standard 12, thereby minimizing linearity errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the ADC operates at low sampling rates with standard clocking, then power consumption is reduced, but linearity errors increase due to prolonged leakage current duration
Solution Approach 1:
The patent applies dynamic clocking by varying the clock frequency during different phases of the conversion process. A higher clock frequency is used during the approximation cycles to minimize leakage current accumulation, while a lower clock frequency is used during the hold phase to reduce power consumption. This dynamic adjustment resolves the contradiction between power savings and linearity accuracy.
Solution Approach 2:
The patent changes the clock frequency parameter based on the conversion phase. By using a first clock frequency (higher) during approximation cycles and a second clock frequency (lower) during the hold phase, the system optimizes both power consumption and linearity accuracy. The parameter change allows the system to minimize leakage effects when critical and reduce power when less critical.
2Measurement precision
If the clock frequency is increased to reduce leakage current effects, then linearity accuracy improves, but the ADC cannot operate at low sampling rates
Solution Approach 1:
The patent implements dynamic clocking that adapts the clock frequency to the required sampling rate. For low sampling rate applications, the system uses a lower overall clock frequency but maintains higher frequency during critical approximation cycles. This dynamic approach preserves linearity accuracy while enabling flexible operation at various sampling rates including low rates.
Solution Approach 2:
The patent uses periodic high-frequency clocking during approximation cycles followed by lower frequency operation during hold phases. This periodic variation in clock frequency allows the system to achieve accurate conversions at low sampling rates by concentrating high-frequency operation only when necessary for linearity, rather than maintaining high frequency continuously.
3Measurement precision
If reset switches are kept closed during approximation cycles to prevent leakage, then linearity errors are reduced, but the conversion time increases
Solution Approach 1:
The patent applies preliminary resetting of the comparator input nodes before the approximation cycles begin. By resetting the nodes to a known state (typically mid-rail voltage) before starting the binary search, the system eliminates the need to keep reset switches closed during approximation. This preliminary action prevents leakage accumulation while allowing the approximation cycles to proceed at optimal speed.
Solution Approach 2:
The patent cushions against leakage effects by performing reset operations beforehand and using leakage compensation techniques during the hold phase. By preparing the comparator inputs in advance and accounting for expected leakage during the hold phase calculations, the system achieves accurate conversions without extending the critical approximation time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces linearity errors by minimizing the duration of leakage current, achieving improved accuracy even at lower sampling rates, as evident from the reduced errors shown in transient response graphs at different clock rates.
Implementation Method 1
A clocking system with a phase locked loop and programmable counter is used to adjust the clock multiplier
Data Source
AI summary
A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.