SAR ADC Code Adjustment for Differential Nonlinearity Reduction
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Solution Overview
Problem
Existing successive approximation analog-digital converters face challenges in reducing differential nonlinearity errors due to element variations in digital-analog converters, particularly static errors which are not effectively addressed by conventional redundancy methods that require additional circuitry, increasing the circuit area.
Innovation Solution
The proposed solution involves a successive approximation AD converter with a comparator circuit, a successive approximation register, an arithmetic circuit, and a switching signal generation circuit that allows for logical operations to adjust the digital signal input to the DA converter, enabling the generation of a second digital signal with a larger or smaller value based on determination bit signals, thereby improving differential nonlinearity without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional redundancy methods are used to address static differential nonlinearity error, then the error correction capability is improved, but the circuit area increases due to additional circuitry
Solution Approach 1:
The patent changes the operational parameters of the existing DA converter by dynamically adjusting the digital code input through logical operations. Instead of adding redundant hardware, the invention modifies the code values presented to the DA converter elements, enabling error correction through parameter variation rather than structural expansion.
Solution Approach 2:
The patent creates a virtual copy of the redundancy function through digital logic operations. Rather than physically duplicating DA converter elements, the invention uses arithmetic circuits to generate alternative code representations that achieve the same error correction purpose, eliminating the need for additional analog circuitry.
2Productivity
If the DA converter conversion speed is increased, then the conversion time is reduced, but the dynamic differential nonlinearity error worsens due to insufficient settling time
Solution Approach 1:
The patent performs preliminary logical operations on the digital code before it is converted to analog form. By pre-adjusting the code values through arithmetic circuits based on predicted error patterns, the system compensates for potential settling issues before they occur, enabling faster conversion without sacrificing accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the conversion result is analyzed and used to adjust subsequent conversion codes. The arithmetic circuit uses determination bit signals to modify the digital input to the DA converter, creating a closed-loop system that continuously optimizes conversion accuracy even at high speeds.
Data Source
AI summary
A successive approximation analog-digital (AD) converter and method performed by the converter are provided. The successive approximation AD converter comprises a digital-analog (DA) converter; a comparator which determines a magnitude relation between an input signal and an output signal of the DA converter; and a successive approximation register which generates a first digital signal based on a determination result. The method comprises: switching an operation selection signal from a first logic to a second logic; performing a logical operation so that a digital signal input to the DA converter has a larger value or a smaller value than the first digital signal, when the operation selection signal has transited to the second logic, based on a portion of the determined first digital signal until transition; and inputting the first digital signal to the DA converter when the operation selection signal is the first logic.