SAR ADC Common-Mode Calibration for Higher SNDR
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Solution Overview
Problem
Successive-approximation register analog-to-digital converters face challenges in reducing signal noise, particularly quantization noise and thermal noise, which degrade the signal-to-noise and distortion ratio (SNDR) of the digital signal due to imperfections in the conversion process.
Innovation Solution
The proposed analog-to-digital converter and method calculate the average value of the signal to determine its partial DC offset and adjust the common-mode voltage, reducing residual noise by generating control signals to adjust the sampling signals during the conversion phase, thereby enhancing the SNDR of the output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the successive-approximation register analog-to-digital conversion process is used, then the digital signal is generated through sampling, comparison, and internal sub-digital-to-analog conversion steps, but quantization noise and thermal noise are introduced due to device imperfections, reducing the SNDR
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal operation. During calibration mode, the ADC determines DC offset values for different input signal ranges and stores them in memory. This preliminary measurement allows the system to compensate for DC offset effects during subsequent normal conversion operations, improving SNDR without affecting the core conversion process.
Solution Approach 2:
The patent implements feedback by using the determined DC offset values to adjust and compensate the conversion process. The calibration results are fed back into the system to correct the residual DC offset effects during normal operation, creating a closed-loop compensation mechanism that continuously improves measurement precision.
2Productivity
If the ADC performs sampling and comparison operations, then digital output is generated, but residual DC offset values remain in the conversion process, degrading signal quality
Solution Approach 1:
The patent measures and determines DC offset values during a calibration phase before normal conversion operations begin. By performing this measurement action in advance, the system prepares compensation data that can be applied during high-speed normal operations without slowing down the conversion process, thus maintaining productivity while improving precision.
Solution Approach 2:
The patent changes the operating parameters by switching between calibration mode and normal mode. During calibration, the system measures DC offset characteristics; during normal operation, it applies the determined offset values to compensate for residual effects. This parameter change approach allows the system to optimize both measurement precision and conversion speed at different operational stages.
Data Source
AI summary
An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.