Differential SAR ADC Dynamic Common-Mode Control at Low Supply Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SAR ADCs fail to operate normally under low supply voltages due to the lack of a safety operating range that meets the requirements for both the input buffer output and comparator input, leading to poor linearity and slower conversion speed.
Innovation Solution
A differential SAR ADC with a dynamic input common-mode voltage control scheme that adjusts the input common-mode voltage of the comparator circuit to different levels during the sample and SAR phases, using common-mode capacitors and switch circuits to decouple the operating ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the supply voltage is lowered to reduce power consumption, then power consumption is reduced, but the ADC fails to operate normally due to insufficient signal swing and lack of safety operating range
Solution Approach 1:
The patent implements dynamic common-mode voltage control that adjusts the common-mode voltage level based on the operational phase (sampling phase vs. conversion phase). During the sampling phase, a first common-mode voltage level is applied to optimize buffer linearity, while during the conversion phase, a second common-mode voltage level is applied to ensure proper comparator operation. This dynamic adjustment allows the ADC to maintain reliable operation across both phases even at low supply voltages, resolving the contradiction between low power consumption and operational reliability.
2Device complexity
If a fixed common-mode voltage is used, then the circuit structure is simple, but the ADC cannot maintain good linearity and fast conversion speed simultaneously under low supply voltage
Solution Approach 1:
The patent employs dynamic common-mode voltage switching between two distinct levels: a first level during the sampling phase to maximize input buffer linearity, and a second level during the conversion phase to optimize comparator performance and conversion speed. This dynamic approach, controlled by phase timing signals, enables the ADC to achieve both good linearity and fast conversion speed under low supply voltage conditions without requiring a completely redesign of the circuit architecture.
Solution Approach 2:
The patent changes the common-mode voltage parameter dynamically based on the operational phase. By switching between a first common-mode voltage level (VCM1) during sampling and a second common-mode voltage level (VCM2) during conversion, the system optimizes different performance parameters at different times - linearity during sampling and conversion speed during the SAR phase - thereby achieving overall high productivity without excessive circuit complexity.
Data Source
AI summary
A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.