Reservoir Capacitor SAR ADC for Common-Mode Offset Rejection
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Solution Overview
Problem
Differential successive approximation routine (SAR) analog-to-digital converters (ADCs) face challenges in tolerating variations in input common mode, requiring additional circuitry that increases space, power consumption, and introduces noise.
Innovation Solution
The implementation of a SAR ADC circuit with weighted bit capacitors and reservoir capacitors, along with a comparator circuit and logic circuitry, allows for simultaneous reduction of differential input voltage and common mode offset discrepancies through successive bit trials and charge application from reservoir capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry is used to translate input common mode to required common mode, then common mode matching is achieved, but device area increases
Solution Approach 1:
The reservoir capacitors serve multiple functions: they store charge for the SAR conversion process and simultaneously provide common mode correction by transferring charge to the bit capacitor when common mode offset is detected. This eliminates the need for separate common mode correction circuitry.
Solution Approach 2:
The system uses its existing reservoir capacitors to correct common mode offset without requiring external or additional correction circuits. The control logic automatically detects common mode offset and directs charge transfer from reservoir capacitors to correct the imbalance, making the system self-correcting.
2Reliability
If additional circuitry is used to translate input common mode to required common mode, then common mode matching is achieved, but power consumption increases
Solution Approach 1:
The reservoir capacitors serve multiple functions: they store charge for the SAR conversion process and simultaneously provide common mode correction by transferring charge to the bit capacitor when common mode offset is detected. This eliminates the need for separate common mode correction circuitry.
Solution Approach 2:
The system uses its existing reservoir capacitors to correct common mode offset without requiring external or additional correction circuits. The control logic automatically detects common mode offset and directs charge transfer from reservoir capacitors to correct the imbalance, making the system self-correcting.
3Reliability
If additional circuitry is used to translate input common mode to required common mode, then common mode matching is achieved, but noise increases
Solution Approach 1:
The reservoir capacitors serve multiple functions: they store charge for the SAR conversion process and simultaneously provide common mode correction by transferring charge to the bit capacitor when common mode offset is detected. This eliminates the need for separate common mode correction circuitry.
Solution Approach 2:
The system uses its existing reservoir capacitors to correct common mode offset without requiring external or additional correction circuits. The control logic automatically detects common mode offset and directs charge transfer from reservoir capacitors to correct the imbalance, making the system self-correcting.
4Reliability
If reservoir capacitor charge is applied to bit capacitors, then common mode offset is reduced, but conversion time increases
Solution Approach 1:
The system performs common mode correction during the SAR conversion process itself, using the reservoir capacitors that are already charged during the sampling phase. The correction is integrated into the conversion workflow rather than being a separate preliminary or post-processing step.
Solution Approach 2:
The common mode correction function is merged with the SAR conversion process. The reservoir capacitors used for normal conversion operations are also utilized for common mode correction, combining two functions into a single integrated process that shares hardware resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the tolerance of SAR ADCs to input variations without the need for additional circuitry, reducing noise and power consumption while ensuring accurate digital conversion.
Implementation Method 1
a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors, and sample a reference voltage onto the reservoir capacitors
Implementation Method 2
apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce the discrepancy between the input common mode offset and the comparator common mode offset
Data Source
AI summary
An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset.