Differential SAR ADC Sampling for Wide Common-Mode Range
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Solution Overview
Problem
Differential SAR ADCs have limited input common-mode range, making them less suitable for applications where input common-mode voltage cannot be controlled, and existing solutions require additional active circuitry that increases current consumption and integrated circuit die area.
Innovation Solution
A method that resets top plate nodes of binary weighted capacitors to a voltage vcm, samples differential voltages while coupling top plates together, and performs sequential SAR analog-to-digital conversion, achieving wide input common-mode range without additional active circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional active circuitry is used to expand input common-mode range, then input common-mode range is improved, but current consumption and integrated circuit die area increase
Solution Approach 1:
The patent extracts and eliminates the need for additional active circuitry (such as common-mode tracking amplifiers and extra switching networks) by using a passive capacitor-based approach. The existing SAR ADC capacitor array is repurposed to track and cancel input common-mode voltage through charge redistribution, removing the harmful dependency on power-consuming active components while maintaining wide input common-mode range.
Solution Approach 2:
The patent substitutes active electronic circuitry (amplifiers, switches) with a passive capacitive mechanism. By using the inherent charge storage capability of the SAR ADC capacitor array and manipulating charge redistribution through controlled switching phases, the system achieves active-common-mode-rejection functionality without any active amplifying elements, thereby eliminating current consumption associated with such circuitry.
2Adaptability or versatility
If additional active circuitry is used to expand input common-mode range, then input common-mode range is improved, but integrated circuit die area increases
Solution Approach 1:
The patent makes the existing SAR ADC capacitor array multi-functional by having it serve both its original conversion function and an additional common-mode tracking function. The same capacitor array that performs the binary-weighted digital conversion also tracks input common-mode voltage variations through charge redistribution, eliminating the need for separate dedicated common-mode tracking circuitry and thus saving integrated circuit die area.
Solution Approach 2:
The patent merges the common-mode tracking function with the existing SAR ADC conversion mechanism. By combining the charge redistribution process used for digital conversion with the charge tracking process for common-mode voltage, the system achieves wide input common-mode range without adding separate physical circuit blocks, thereby minimizing integrated circuit die area occupation.
3Use of energy by moving object
If conventional SAR ADC is used without additional circuitry, then current consumption is reduced, but input common-mode range is limited
Solution Approach 1:
The patent applies preliminary action by performing a reset phase before the actual conversion phase. During this reset phase, all capacitors in the SAR ADC array are pre-charged to a common reference voltage, establishing a known initial charge state. This preliminary charging enables the subsequent conversion phase to accurately track input common-mode voltage variations without requiring additional active circuitry, thus maintaining low current consumption while expanding input common-mode range.
Solution Approach 2:
The patent implements periodic action through cyclic switching phases (reset phase, conversion phase, hold phase) that repeatedly charge and redistribute charges among the capacitor array. This periodic charge redistribution mechanism continuously tracks input common-mode voltage variations, enabling wide input common-mode range to be achieved through time-multiplexed operation rather than through power-consuming continuous active circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables rail-to-rail input common-mode capability with reduced power consumption and no additional circuit overhead, allowing for improved performance in applications with uncontrolled input common-mode voltage.
Implementation Method 1
a plurality of binary weighted capacitors
Data Source
AI summary
A differential successive approximation register (SAR) analog-to-digital converter (ADC) with wide input common-mode range adds one step to its conversion process. No additional circuitry is required for full rail-to-rail common mode voltage operation. In a first step the top-plate nodes vcp and vcn may be reset to a fixed voltage vcm. Then in a next step sampling may be performed while leaving vcp and vcn floating but shorted. Whereby a single node vx is formed, which provides for simple capacitive voltage division. Thereafter a standard sequential SAR bit-by-bit analog-to-digital conversion is performed. the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit.