SAR ADC Comparator Calibration for PVT-Stable High-Speed Conversion

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Solution Overview

Problem

SAR ADCs face performance issues due to Process, Voltage, and Temperature (PVT) variations and input common mode voltage (Vcm) bias conditions, leading to degraded speed, precision, and accuracy in high-speed data processing applications.

Innovation Solution

A calibration scheme for SAR ADCs that includes a comparator topology and adaptive feedback technique to mitigate performance issues by adjusting bias current (Ibias) and input common mode voltage (Vcm), using a replica circuit and calibration logic to optimize performance across varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If SAR ADC operates at high speed for real-time data processing, then productivity is improved, but measurement precision deteriorates due to PVT variations

Engineering Contradiction:

Improvedata processing speedVSAvoidsignal conversion accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent dynamically adjusts comparator bias current and common mode voltage levels based on detected PVT conditions to maintain conversion accuracy across different operating speeds and environmental conditions

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system uses calibration logic to detect actual comparator performance and feed back adjustment signals to modify bias currents and voltage levels, creating a closed-loop control system that maintains precision despite speed variations

Inventive Principle:

Principle #23Feedback

2Productivity

If comparator bias current is increased to improve conversion speed, then productivity is improved, but use of energy worsens

Engineering Contradiction:

Improveconversion speedVSAvoidcomparator power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic bias current adjustment where the comparator bias current is varied based on operating conditions and required conversion speed, rather than using a fixed high current to always ensure fast conversion

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the bias current parameter adaptively based on detected performance margins and required conversion speed, reducing current when full speed is not needed and increasing it only when performance margins indicate slower conversion

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If calibration circuitry is added to compensate for PVT variations, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improveconversion accuracyVSAvoidcircuit structure

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The calibration system is divided into separate functional blocks: PVT sensing circuitry, calibration logic, and adjustable bias current sources, allowing independent optimization and modular integration into the SAR ADC structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The calibration system uses the SAR ADC's own operating conditions and performance margins to automatically adjust its own bias parameters without requiring external calibration equipment or complex external control circuits

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20260039309A1Successive approximation register analog to digital converter with comparator performance calibration

Publication Date: 2026.02.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Systems and methods are related to device including but not limited to a SAR ADC. The device includes a first digital to analog conversion (DAC) circuit including first capacitors. The digital to analog conversion (DAC) circuit is configured to adjust a first input voltage in response to a first control signal. The device also includes a first comparator configured to receive an adjusted input voltage from the digital to analog conversion (DAC) circuit. The first control signal is provided in response to a target input voltage and a sensed input voltage and adjusts the first input voltage using the first capacitors.