SAR ADC Comparator Control Without Extra Logic Gates
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Solution Overview
Problem
Conventional successive approximation register (SAR) analog-to-digital converters (ADCs) face issues with operating speed and power consumption due to the mechanism used for generating control signals.
Innovation Solution
The proposed SAR ADC architecture eliminates the need for additional logic gates by directly coupling the control signal to the comparison circuit, utilizing a digital-to-analog converter (DAC), a comparison circuit, and a logic circuit that executes logic conversions using XOR or NOR gates to enable or disable the ADC, thereby reducing power consumption and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a control signal mechanism is used to enable or disable the SAR ADC, then the ADC can be controlled, but the operating speed is affected and additional power is consumed
Solution Approach 1:
The patent extracts and eliminates the additional logic gates (AND gate and inverter) from the conventional control signal mechanism. By directly coupling the control signal to the comparison circuit, the design removes the unnecessary logic stages that were slowing down the operating speed while maintaining the enable/disable control capability.
Solution Approach 2:
The patent introduces a direct coupling mechanism as an intermediary between the control signal and the comparison circuit, replacing the complex logic gate chain. This direct path allows the control signal to efficiently enable or disable the ADC without introducing additional delay stages.
2Ease of operation
If a control signal mechanism with additional logic gates is used, then the ADC can be enabled or disabled, but power consumption increases
Solution Approach 1:
The patent removes the additional logic gates (AND gate and inverter) from the control signal path. These eliminated gates were consuming unnecessary power, and their removal directly reduces the overall power consumption of the ADC while preserving the control functionality.
Solution Approach 2:
The comparison circuit is designed to be directly controllable by the control signal without requiring additional logic gates to service the control function. This self-service approach eliminates the power-consuming intermediate logic stages.
3Ease of operation
If additional logic gates are used for control signal processing, then the ADC can be controlled, but the operation time increases
Solution Approach 1:
The patent extracts and removes the additional logic gates (AND gate and inverter) that were increasing the operation time. By eliminating these unnecessary logic stages, the control signal can propagate directly to the comparison circuit, significantly reducing the overall operation time while maintaining control capability.
Solution Approach 2:
The patent implements a direct coupling path that allows the control signal to skip through the intermediate logic gates and directly reach the comparison circuit. This rushing through approach minimizes the time delay introduced by logic gate processing.
Data Source
AI summary
A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.