SAR ADC Gain Control Using Comparator Feedback at High Speed

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Solution Overview

Problem

High-speed analog-to-digital conversion technologies face challenges in addressing amplitude attenuation due to phase differences between input signals and sampling clocks, as well as interference from undesired signals, leading to variations in sample amplitudes and frequency offsets, which affect signal quality and distortion.

Innovation Solution

The implementation of a successive approximation register (SAR) analog-to-digital converter (ADC) with automatic gain control (AGC) logic that utilizes a charge redistribution digital-to-analog converter (DAC) to generate a digital comparator signal, allowing the AGC logic to adjust gain based on both composite average and peak amplitudes, thereby compensating for amplitude and frequency offsets across multiple samples.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed sampling is performed, then conversion speed is improved, but amplitude attenuation and distortion increase due to phase differences between input signals and sampling clocks

Engineering Contradiction:
Improveconversion speedVSAvoidamplitude accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent implements automatic gain control (AGC) logic that receives digital comparator signals from the SAR ADC and generates gain control signals based on the detected signal amplitudes. This feedback mechanism dynamically adjusts the gain of the input signal to compensate for amplitude attenuation caused by high-speed sampling phase differences, thereby maintaining measurement precision while preserving conversion speed

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts the gain control signal in response to varying signal conditions during the sampling process. The AGC logic continuously monitors signal amplitudes and modifies the gain accordingly, enabling the system to adapt to phase differences and frequency offsets that occur at high conversion speeds, thus resolving the contradiction between speed and precision

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If automatic gain control is implemented to compensate for amplitude variations, then signal quality is improved, but device complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent reuses existing components within the SAR ADC architecture for multiple functions. The digital comparator, originally used for conversion decisions, is also employed to generate signals for the AGC logic. This multi-functionality approach enables automatic gain control and amplitude compensation without adding separate dedicated hardware circuits, thereby limiting the increase in device complexity while still improving signal quality

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If gain adjustment is performed based on multiple samples, then frequency offset compensation is improved, but conversion time increases

Engineering Contradiction:
Improvefrequency offset compensationVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs gain adjustments based on composite average amplitudes calculated from multiple samples taken during the sampling process. By using preliminary amplitude information from earlier samples to guide subsequent gain adjustments, the system achieves frequency offset compensation without requiring a complete additional conversion cycle, thus minimizing the time penalty while improving measurement precision

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8754800B2Methods and arrangements for high-speed analog-to-digital conversion
Publication Date: 2014.06.17 APPLE INC
  • US8754800B2 patent drawing
  • US8754800B2 patent drawing
  • US8754800B2 patent drawing

AI summary

Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes.