SAR ADC Comparator Gating to Eliminate Forbidden-State Bit Errors
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face challenges in operating at high speeds due to the occurrence of probabilistic errors, specifically the forbidden state where the SAR logic circuitry writes the same logical value to the conversion result twice, leading to erroneous bit values and subsequent bits being affected.
Innovation Solution
The implementation of digital feedback circuitry that logically gates the comparator outputs using opposite polarity information, preventing the SAR logic circuitry from writing the same bit value twice by utilizing NAND gates and asynchronous clock generation, thereby eliminating the forbidden state without increasing complexity, power, or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SAR ADC operates at high speeds, then conversion speed is improved, but probabilistic errors occur due to forbidden state
Solution Approach 1:
The patent implements digital feedback circuitry that monitors the comparator outputs and uses opposite polarity information to gate the SAR logic circuitry operations. This feedback mechanism detects when a forbidden state is approaching and prevents the probabilistic error from occurring, allowing high-speed operation without sacrificing reliability
Solution Approach 2:
The patent introduces digital feedback circuitry as an intermediary between the comparator outputs and the SAR logic circuitry. This intermediary uses NAND gates and opposite polarity information to mediate the control signals, preventing direct writing of the same bit value twice while maintaining high-speed operation
2Reliability
If digital feedback circuitry is added to eliminate forbidden state, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent changes the logical parameters of the feedback circuitry by using opposite polarity information and NAND gate logic. This parameter change allows the feedback mechanism to be implemented with simple digital logic elements rather than complex analog circuitry, maintaining low complexity while achieving high reliability
Solution Approach 2:
The patent uses simple, inexpensive digital logic elements (NAND gates) to implement the feedback circuitry. These simple logic components are far less complex than alternative solutions, providing reliable error elimination without significantly increasing device complexity or cost
Data Source
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AI summary
Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.