Redundant SAR ADC Control Codes for High-Speed Conversion
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Solution Overview
Problem
Successive approximation register (SAR) A/D converters experience a decrease in operation speed due to the introduction of a delay path for redundancy, which becomes more significant as the number of bits increases, hindering high-speed conversion.
Innovation Solution
The SAR A/D converter incorporates a logic unit that generates two candidate control codes for the next cycle by adding or subtracting a weight, allowing immediate supply of the control code after comparison signal determination, thereby reducing calculation delay and maintaining high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay path of addition and subtraction is inserted into the loop of a successive approximation register to provide redundancy, then the reliability of the A/D converter is improved, but the operation speed decreases
Solution Approach 1:
The patent pre-calculates two candidate control codes (first value by addition, second value by subtraction) before the comparison signal is determined. This preliminary action stores the results in advance, eliminating the need for real-time calculation during the critical comparison phase, thus maintaining high operation speed while providing redundancy for reliable conversion even when comparison errors occur
2Measurement precision
If the number of bits of the SARADC is increased to achieve higher resolution, then the measurement precision is improved, but the operation speed decreases more significantly
Solution Approach 1:
By pre-calculating and storing candidate control codes before the comparison signal determination, the patent eliminates real-time calculation delays. This approach allows the converter to maintain high operation speed even when processing increased bit depths for higher resolution conversions
3Reliability
If a delay path is inserted to provide redundancy for error correction, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent implements redundancy by pre-calculating two candidate control codes using addition and subtraction operations, storing them in advance. This approach provides error correction capability without requiring complex real-time computation circuits, thus improving reliability while controlling device complexity
Solution Approach 2:
The patent creates redundant information by generating two candidate control codes (first and second values) from the same input data through different calculation paths (addition and subtraction). This copying approach provides backup information for error correction without significantly increasing overall system complexity
Data Source
AI summary
A successive approximation register A/D converter (SARADC) has redundancy. An analog unit samples an analog input voltage and generates a comparison signal indicating a magnitude relationship between a threshold voltage corresponding to a control code and the analog input voltage. A logic unit generates, in an i-th (i≥1) cycle, a first value obtained by adding a weight of an (i+1)-th cycle to a control code of the i-th cycle and a second value obtained by subtracting the weight of the (i+1)-th cycle from the control code of the i-th cycle. When a comparison signal of the cycle is determined, the logic unit supplies one of the first value and the second value corresponding to the comparison signal to the analog unit 110 as a control code of the (i+1)-th cycle.