SAR ADC Cooperative Thresholding for Fast Error-Corrected Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive approximation analog-to-digital converters (SAR ADCs) face challenges in achieving high conversion accuracy and speed while maintaining low cost and power consumption, due to noise and error issues that limit bit resolution and require redundant bit trials, and existing multi-engine approaches result in large die area and incomplete error correction.
Innovation Solution
The proposed solution involves a SAR ADC architecture with multiple conversion engines that operate in cooperative and independent modes, using a controller to adjust threshold voltages and introduce redundancy, allowing for simultaneous determination of multiple bits per trial and inbuilt error correction, reducing noise impact and increasing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple conversion engines operate independently to correct errors, then accuracy is improved, but die area increases
Solution Approach 1:
The patent merges multiple conversion engines to operate cooperatively during a first phase, allowing them to share resources and determine multiple bits per trial together. This cooperative operation achieves error correction and improved accuracy without requiring each engine to be fully independent, thereby reducing the total die area compared to fully independent engine architectures.
Solution Approach 2:
The system dynamically switches between two operational phases: a first phase where engines operate cooperatively to determine multiple bits per trial with shared resources, and a second phase where engines operate independently for final error correction. This dynamic phase switching allows the system to achieve high accuracy through independent operation when needed while using cooperative operation to reduce overall die area.
2Measurement precision
If serial bit trials are performed to ensure accuracy, then measurement precision is improved, but conversion speed deteriorates
Solution Approach 1:
The conversion process is segmented into two distinct phases: a first phase that determines multiple bits per trial using cooperative engine operation, and a second phase that performs final error correction. This segmentation allows the majority of the conversion to be completed rapidly in parallel, with only minimal serial trials needed for correction, thereby significantly improving conversion speed while maintaining accuracy.
Solution Approach 2:
The system performs partial bit determination in the first phase using cooperative engines, achieving most of the conversion accuracy without completing all bit trials. The second phase then performs only the necessary corrective action to eliminate remaining errors. This partial action approach avoids the need for complete serial bit trials, thereby improving conversion speed.
3Reliability
If redundant bit trials are performed to correct errors, then reliability is improved, but productivity deteriorates
Solution Approach 1:
The first phase of cooperative engine operation performs preliminary bit determination that inherently provides error correction capability through the collaborative comparison of multiple engines. This preliminary action establishes a reliable baseline conversion result before the second phase, reducing the need for extensive redundant trials and thereby maintaining high productivity.
Solution Approach 2:
The system uses feedback from the cooperative engine operation in the first phase to inform the second phase. The results and error patterns observed during cooperative operation guide the corrective action in the second phase, allowing redundant trials to be targeted and minimized rather than performed exhaustively, thereby maintaining high conversion speed while ensuring reliability.
Data Source
AI summary
The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial. The plurality of conversion engines operate in a second phase of the conversion by inputting the produced M threshold voltages into the associated inputs of the M comparators such that the plurality of conversion engines operate independently so that fewer bits are determined from the sampled signal during each successive approximation trial then were determined during the first phase. A result obtained from at least one of the plurality of conversion engines is then outputted.