SAR ADC Cycle Adaptation Using Input Voltage Thresholds
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly successive approximation register (SAR) ADCs, are power inefficient when the input voltage varies over a small range, as they perform full conversion cycles regardless of the voltage level.
Innovation Solution
The proposed solution involves an input-adaptive analog-to-digital conversion method where the number of conversion cycles is adjusted based on the input voltage level. A threshold voltage is used to determine whether to resolve all bits or only the last few bits, reducing power consumption when the input voltage is within a small range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full conversion cycles are performed regardless of input voltage level, then measurement precision is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic conversion cycle adjustment where the ADC adapts the number of conversion cycles based on the input voltage level. When the input voltage is within a small range (below threshold), fewer conversion cycles are performed. When the input voltage exceeds the threshold, full conversion cycles are executed. This dynamic adaptation resolves the contradiction by making the conversion process flexible rather than fixed, maintaining precision when needed while reducing power consumption during normal operation.
Solution Approach 2:
The patent changes the parameter of conversion cycle count based on input voltage conditions. By monitoring the input voltage level and adjusting the number of conversion cycles accordingly, the system optimizes the balance between measurement precision and power consumption. The threshold voltage serves as a reference point for this parameter change, allowing the ADC to switch between different operational modes.
2Use of energy by moving object
If the number of conversion cycles is reduced for small voltage ranges, then power efficiency improves, but measurement precision may deteriorate
Solution Approach 1:
The patent employs feedback mechanisms where the ADC continuously monitors the input voltage level and uses this information to determine the appropriate number of conversion cycles. The threshold voltage comparison provides feedback that triggers different conversion modes. This feedback loop ensures that measurement precision is maintained when the input voltage exceeds the threshold, while power efficiency is improved when the voltage remains within the small range, resolving the contradiction through intelligent decision-making based on real-time conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the average number of conversion cycles per analog-to-digital conversion, thereby increasing power efficiency, especially when the input voltage resides within a small voltage range most of the time.
Implementation Method 1
The capacitive DAC includes binary-weighted capacitors, wherein the binary-weighted capacitors include a most significant bit (MSB) capacitor and lower-order capacitors
Data Source
AI summary
Aspects of the present disclosure provide input-adaptive analog-to-digital conversion in which the number of conversion cycles used to convert an input signal into a digital signal is adapted based on the level (i.e., amplitude) of the input voltage. In certain aspects, the input voltage is compared with one or more threshold voltages, and the number of conversion cycles is determined based on the comparison. In certain aspects, a most significant bit (MSB) capacitor in a capacitive digital-to-analog (DAC) is split into two or more capacitors to provide the one or more threshold voltages.