SAR ADC Timing Control for Capacitance DAC Settling
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Solution Overview
Problem
Successive approximation type A/D converters face inefficiencies due to non-uniform settling times in the capacitance DAC, leading to excessive allocation of conversion clock periods and reduced conversion speed, as existing solutions fail to accurately account for changes in capacitance values.
Innovation Solution
Incorporating a comparator operation signal generation circuit that predicts the settling time of the capacitance DAC using a capacitance element with equal characteristics, allowing for precise timing of comparison operations and reducing unnecessary settling time allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform conversion clock period is allocated to all bits, then the settling time is sufficient for the highest bit, but excessive time is wasted for lower bits, reducing conversion speed
Solution Approach 1:
The patent applies dynamics by making the conversion clock period variable rather than uniform. The clock period is dynamically adjusted based on the bit position being converted, with higher bits receiving longer periods and lower bits receiving shorter periods. This dynamic timing strategy matches the actual settling time requirements of each bit, eliminating wasted time while ensuring sufficient settling time for accurate conversion.
2Reliability
If a margin is added to the conversion clock period to cover capacitance value changes, then reliability is improved, but excessive settling time is allocated, reducing conversion speed
Solution Approach 1:
The patent applies local quality by allocating different clock periods to different bit positions based on their specific settling time requirements. Instead of using a uniform period with a large margin for all bits, each bit receives a locally optimized period that matches its actual needs. This ensures conversion accuracy for each bit without unnecessarily extending the overall conversion time.
3Productivity
If the settling time for each bit is reduced to match actual requirements, then conversion speed is improved, but insufficient time may be allocated causing conversion errors
Solution Approach 1:
The patent uses dynamic clock period adjustment where the period for each bit is precisely tailored to its settling time requirements. Higher bits that require more time receive longer periods, while lower bits that settle faster receive shorter periods. This dynamic allocation ensures that each bit receives exactly the time it needs for accurate conversion, maximizing speed without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more accurate prediction of settling times for each bit, optimizing the conversion process and achieving higher speeds by eliminating excessive settling time allocations, thereby enhancing the overall efficiency of the A/D converter.
Implementation Method 1
a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element
Data Source
AI summary
An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.