Asynchronous SAR ADC Clock Control With Variable Delay Feedback

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Solution Overview

Problem

SAR ADCs are inefficient in utilizing the available time for signal conversion due to their reliance on fixed clock cycles, leading to suboptimal performance and potential rollover issues across varying process, voltage, and temperature conditions.

Innovation Solution

A self-modulating clocked delay loop and control system that adjusts the pulse width dynamically based on detected edges to maximize the use of available time for conversion, utilizing a variable delay circuit and edge selector to optimize conversion time without rollover.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a fixed clock cycle is used to control SAR ADC conversion, then the device operation is simple and reliable, but the conversion time utilization is inefficient and performance degrades under varying conditions

Engineering Contradiction:

Improveconversion time utilizationVSAvoidclock control mechanism

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic clock control mechanism where the pulse generator adjusts pulse width based on detected edge count. The system transitions from fixed clock cycles to variable pulse widths that adapt to actual conversion needs, maximizing time utilization while maintaining manageable complexity through feedback-based control

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system uses edge detection feedback to monitor the number of conversion edges and dynamically adjusts the pulse width accordingly. The edge selector and pulse generator form a feedback loop that optimizes conversion time utilization by comparing detected edges against expected values and adjusting timing parameters in real-time

Inventive Principle:

Principle #23Feedback

2Loss of time

If the pulse width is increased to maximize conversion time utilization, then more available time is utilized for conversion, but frequency variations and power consumption increase

Engineering Contradiction:

Improveavailable conversion timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The system applies partial action by using only the necessary pulse width required for conversion completion. Rather than continuously applying maximum pulse width, the system adjusts pulse duration to match actual conversion needs, utilizing edge detection to determine when conversion is complete and stopping pulse generation accordingly, thus reducing unnecessary energy consumption

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent dynamically changes the pulse width parameter based on detected edge count and conversion progress. By adjusting this critical timing parameter in response to actual conversion conditions, the system maximizes time utilization while minimizing energy waste from excessive pulsing

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the conversion time is extended to accommodate slow conversions, then conversion completeness is improved, but rollover issues occur when conversion is too fast

Engineering Contradiction:

Improveconversion completenessVSAvoidperformance consistency across conditions

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system dynamically adjusts pulse width based on real-time edge detection, allowing it to adapt to varying conversion speeds. When conversion is slow, longer pulses ensure completeness; when conversion is fast, shorter pulses prevent rollover. This dynamic adaptation maintains reliability across all operating conditions

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Edge detection feedback enables the system to monitor conversion progress and adjust timing accordingly. The feedback mechanism detects when conversion completes and adjusts pulse width to match actual needs, preventing both incomplete conversions and rollover issues from excessive pulsing

Inventive Principle:

Principle #23Feedback

4Productivity

If a variable delay circuit is added to optimize pulse width, then conversion time utilization improves, but device complexity increases

Engineering Contradiction:

Improvetime utilization efficiencyVSAvoidcircuit structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The variable delay circuit acts as an intermediary between the pulse generator and the SAR ADC, providing fine-grained timing control without requiring complete redesign of the core conversion architecture. This modular approach improves time utilization while containing complexity in a dedicated timing control block

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12537533B2Asynchronous successive approximation register with asynchronous clock control

Publication Date: 2026.01.27 SKYWORKS SOLUTIONS INC

AI summary

A system for determining a variable delay provided to a pulse generator for a successive approximation register analog-to-digital converter (SAR ADC) is presented. The system comprises a delay loop coupled to the pulse generator, the delay loop having a variable delay circuit configured to provide the variable delay to the pulse generator, and an edge selector coupled to the delay loop, the edge selector being configured to determine the variable delay provided to the pulse generator.