SAR ADC One-Gate-Delay Logic for Faster Successive Approximation
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Solution Overview
Problem
Existing successive-approximation register analog-to-digital converters (SAR ADCs) face challenges in speeding up the successive approximation process, which limits their high-speed performance.
Innovation Solution
The design incorporates a SAR ADC configuration with a digital-to-analog converter (DAC) and a comparator, utilizing a one-gate-delay circuit, specifically an OR-AND-INVERTER (OAI) or AND-OR-INVERTER (AOI) gate, within the SAR logic circuit to reduce delay between the comparator and the DAC, forming a high-speed loop for successive approximation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SAR ADC configuration is used, then the circuit structure is simple, but the approximation speed is limited
Solution Approach 1:
The patent introduces a one-gate-delay circuit that performs preliminary action by pre-positioning the comparator output signal one gate cycle ahead of the DAC control input. This timing advancement allows the approximation process to proceed one gate delay faster than conventional designs, directly improving approximation speed without requiring a complete redesign of the SAR ADC architecture.
Solution Approach 2:
The patent introduces a one-gate-delay circuit as an intermediary component between the comparator and the DAC. This intermediary element buffers and times the signal transfer, allowing the system to achieve higher speed by decoupling the comparator switching speed from the DAC response time, thereby resolving the speed limitation while maintaining structural simplicity.
2Reliability
If more gates are used in the delay circuit, then the signal propagation is more stable, but the delay increases
Solution Approach 1:
The patent optimizes the delay circuit by changing the parameter of gate count from multiple gates to exactly one gate. This parameter change achieves the minimum necessary delay to stabilize signal propagation while minimizing time loss. The single-gate configuration provides sufficient signal conditioning and timing alignment without introducing excessive delay that would slow down the approximation process.
Data Source
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AI summary
A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.