SAR ADC Comparator Delay Tuning for Sampling Noise Cancellation
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Solution Overview
Problem
Existing SAR analog-to-digital converters (ADCs) reduce sampling noise only in narrow use cases with predetermined input signal frequencies and preamplifier bandwidths, failing to accommodate varying input signal frequencies and source impedances, and face issues with preamplifier saturation and power consumption.
Innovation Solution
Implementing a programmable delay across the preamplifier in the comparator of the SAR ADC, allowing the delay to be adjusted based on current operating parameters such as sampling frequency, source resistance, and power mode to reduce sampling noise across a range of use-cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed delay is used across the preamplifier, then sampling noise is reduced for narrow use cases with predetermined input signal frequency, but the ADC fails to accommodate varying input signal frequencies and source impedances
Solution Approach 1:
The patent implements a programmable delay unit that can dynamically adjust the delay time based on the input signal frequency and source impedance. Instead of using a fixed delay, the system allows the delay parameter to change adaptively, resolving the contradiction between achieving noise reduction for specific frequencies and accommodating varying operating conditions. The delay unit is controlled by a controller that selects appropriate delay values based on detected signal characteristics.
2Use of energy by stationary object
If a long delay time is used across the preamplifier, then the bandwidth requirement and power consumption are reduced, but the preamplifier may saturate
Solution Approach 1:
The patent applies parameter changes by making the delay time a variable parameter that can be adjusted based on operating conditions. The controller selects from multiple delay values (e.g., first delay value for higher power mode, second delay value for lower power mode) to optimize the balance between power consumption and saturation risk. This allows the system to adapt the delay parameter to prevent saturation while managing power usage.
3Reliability
If a short delay time is used across the preamplifier, then the likelihood of preamplifier saturation is reduced, but the bandwidth requirement and power consumption increase
Solution Approach 1:
The system dynamically adjusts the delay time based on real-time operating conditions including input signal frequency, source impedance, and power mode. The controller monitors these parameters and selects the appropriate delay value to maintain reliability while optimizing power consumption. This dynamic adjustment resolves the contradiction by allowing the delay to be short when needed for saturation avoidance and long when power efficiency is prioritized.
4Measurement precision
If a fixed delay is programmed into the ADC, then the delay is optimized for a specific input signal frequency, but it does not reduce sampling noise for frequencies twice the expected frequency or for higher impedance sources
Solution Approach 1:
The patent implements a universal delay unit that can serve multiple functions by accepting different delay values based on operating conditions. The programmable delay unit replaces the fixed delay, allowing the same hardware to be optimized for different input signal frequencies and source impedances. The controller selects from multiple delay configurations to achieve noise reduction across various operating scenarios, making the ADC versatile rather than frequency-specific.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.