SAR ADC Delta Modulation With DEM for Noise and Linearity
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Solution Overview
Problem
Successive approximation register analog to digital converters (SAR ADCs) face errors due to noise and capacitor mismatch, leading to degraded linearity in digital output.
Innovation Solution
The implementation of incremental delta modulation (IDM) and dynamic element matching (DEM) operations in SAR ADCs, using capacitors grouped into multiple sets, where IDM generates multiple outputs over cycles and DEM selects different capacitor sets for each cycle, with the averaged outputs being added to the digital output to compensate for errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a SAR ADC uses a binary weighted capacitive DAC, then the conversion process can be completed in a single clock cycle, but noise and capacitor mismatch cause degradation in linearity and signal-to-noise ratio
Solution Approach 1:
The patent segments the conversion process into multiple phases: a first conversion phase using binary weighted capacitors for speed, and a second conversion phase using segmented capacitors for precision. By dividing the conversion process into separate stages with different capacitor configurations, the system achieves both fast conversion and high linearity without compromising either requirement.
2Measurement precision
If multiple capacitor sets are used to generate multiple outputs for averaging, then noise and mismatch errors are reduced, but the device complexity increases
Solution Approach 1:
The patent merges two different conversion approaches into a single unified system: the first conversion phase uses binary weighted capacitors while the second phase uses segmented capacitors. By combining these two conversion modes within one ADC architecture and averaging their outputs, the system achieves noise reduction and error compensation without requiring completely separate converter circuits.
Solution Approach 2:
The patent employs periodic switching between two capacitor configurations: binary weighted capacitors for the first conversion phase and segmented capacitors for the second conversion phase. This periodic alternation between different capacitor arrangements allows the system to exploit the advantages of each configuration at appropriate times, achieving both speed and precision through time-multiplexed operation.
Data Source
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AI summary
A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.