SAR ADC Digital Arithmetic Unit for CMOS Image Sensor Signal Processing
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Solution Overview
Problem
Analog to digital converters for image signals often require separate capacitors to store reset and offset voltages, which occupy space and increase convergence time, and can introduce error voltages due to insufficient buffer driving ability and transmission line resistance.
Innovation Solution
An analog to digital converting device that integrates a SAR analog to digital converter and digital arithmetic unit, eliminating the need for separate capacitors by using a feedback loop and digital correlated double sampling logic to calculate differences between reset and signal voltages, thereby reducing device size and convergence time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate capacitors are used to store reset voltage and offset voltage, then the converter can perform analog signal storage and processing, but the device area increases and convergence time is extended
Solution Approach 1:
The patent merges the functions of reset voltage storage and offset voltage storage into a single capacitor. The capacitor is first used to store the reset voltage during the reset phase, then subsequently used to store the offset voltage during the signal processing phase. This consolidation eliminates the need for separate capacitors, reducing device area while maintaining the necessary signal processing capabilities through temporal multiplexing of the capacitor's function.
Solution Approach 2:
The single capacitor is designed to perform multiple functions sequentially: it serves as a reset voltage storage element during the reset phase, then transitions to serving as an offset voltage storage element during the signal conversion phase. This multi-functional design allows the same hardware component to fulfill different roles at different times, thereby reducing the total component count and device area without compromising processing accuracy.
2Reliability
If separate capacitors are used to store reset voltage and offset voltage, then voltage storage is achieved, but convergence time increases
Solution Approach 1:
By combining the reset voltage storage and offset voltage storage functions into a single capacitor, the patent eliminates the need for two separate convergence processes. The capacitor undergoes one convergence process per phase (reset phase and signal phase), rather than requiring simultaneous convergence of multiple capacitors. This reduces the overall convergence time while maintaining voltage storage stability through the capacitor's inherent electrical characteristics.
Solution Approach 2:
The capacitor operates in periodic phases: during the reset phase, it stores and converges the reset voltage; during the signal phase, it stores and converges the offset voltage. This periodic operation allows the capacitor to complete one convergence process per phase transition, rather than requiring multiple capacitors to converge simultaneously, thereby reducing the total convergence time while maintaining stability through the regular timing of phase transitions.
3Device complexity
If buffer driving ability is insufficient and transmission line resistance is present, then device complexity is reduced, but error voltage is introduced
Solution Approach 1:
The patent introduces a feedback mechanism where the offset voltage is measured and stored in the capacitor, then fed back into the conversion process to compensate for errors. The digital arithmetic unit calculates the offset voltage based on the capacitor's stored value and applies the appropriate correction to the final digital output. This feedback approach allows the use of a simpler converter structure without buffer amplifiers while maintaining signal accuracy through mathematical compensation of the transmission line resistance effects.
Solution Approach 2:
The patent changes the approach from hardware-based error correction (using buffered amplifiers with high driving ability) to software/mathematical-based correction. By measuring the actual offset voltage parameter introduced by transmission line resistance and using digital arithmetic to compensate for it, the system achieves the same accuracy goal through parameter measurement and calculation rather than through complex hardware buffering, thereby reducing device complexity while maintaining precision.
Data Source
AI summary
An analog to digital converting device includes an analog to digital converting unit suitable for converting an image signal into a digital signal; and a digital arithmetic unit suitable for calculating a difference between a reset voltage and a signal voltage, which correspond to the digital signal.