SAR ADC Digital Correction for Metastability Error Propagation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive approximation register (SAR) ADCs face limitations in sampling frequency due to their iterative nature, leading to metastability issues and potential bit errors, especially at high resolutions and clock frequencies, which can result in measurable bit error rates that communication systems cannot tolerate.
Innovation Solution
The implementation of an error detection and correction mechanism that ceases iteration when the comparator is indecisive, using a digital circuit to detect error conditions and output the previous iteration value, thereby preventing error propagation and relaxing timing requirements for the comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SAR ADC operates at high clock frequencies to achieve higher sampling rates, then productivity is improved, but reliability deteriorates due to metastability issues and bit errors
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction before the erroneous data propagates through the system. The error detection circuit identifies metastability issues and bit errors in advance, and the error correction circuit fixes these errors before they affect the final conversion output, thus maintaining reliability at high sampling frequencies
Solution Approach 2:
The patent implements feedback by using the error detection circuit to monitor the comparator output and feed this information back to the error correction circuit. This feedback mechanism allows the system to dynamically adjust and correct errors that occur during high-speed operation, resolving the contradiction between high productivity and maintained reliability
2Measurement precision
If the resolution of the SAR ADC is increased to achieve higher precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction function into separate, modular circuit blocks including error detection circuits, error correction circuits, and valid data detection circuits. This segmentation allows high-resolution conversion while managing complexity through functional decomposition, making the system more maintainable and easier to implement
Solution Approach 2:
The patent introduces intermediary error correction circuits that act as mediators between the comparator and the digital output. These intermediary circuits handle the complex error correction tasks, allowing the main SAR ADC structure to remain relatively simple while still achieving high measurement precision through the added error correction layer
3Measurement precision
If the iterative conversion process continues until convergence to achieve high precision, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by detecting errors during the iterative conversion process and ceasing iteration when errors are detected rather than continuing until full convergence. This preliminary error detection prevents wasted conversion cycles, reducing loss of time while maintaining measurement precision through subsequent error correction
Solution Approach 2:
The patent implements feedback by monitoring the convergence process and using error detection signals to feedback control the iteration termination. When the error detection circuit identifies that convergence is not occurring or errors are present, the feedback mechanism stops further iteration, thereby reducing conversion time while maintaining precision through error correction
Data Source
Figure 1
Figure 2
Figure 3-1
AI summary
A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.