SAR ADC Digital Trimming Without Physical Capacitor Matching
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Solution Overview
Problem
High-resolution analog-to-digital converters (ADCs) using successive approximation face challenges in achieving precise capacitance matching, leading to convergence issues due to capacitor mismatch, which requires complex trimming processes increasing production costs and chip area.
Innovation Solution
The ADC incorporates dynamic error correction steps and fine tuning capacitors to adjust voltage levels, allowing for error compensation and convergence without the need for physical trimming, using error correction capacitors and arithmetic stages to digitally correct static mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical trimming procedures (laser trimming or switch-based trimming with memory) are used to correct capacitor mismatch, then manufacturing precision of capacitance values is improved, but device complexity and production cost increase
Solution Approach 1:
The patent replaces physical/mechanical trimming procedures (laser trimming or switch-based trimming) with a digital correction method. Instead of physically modifying capacitors or using complex switch networks, the invention uses digital arithmetic operations to compensate for capacitor mismatch errors, thereby reducing device complexity while maintaining manufacturing precision
Solution Approach 2:
The patent changes the correction approach from physical parameter modification (capacitor value trimming) to digital parameter adjustment (adding correction values to the digital output word). This allows the same precision to be achieved through software/digital means rather than physical trimming processes
2Manufacturing precision
If physical trimming procedures are used to correct capacitor mismatch, then manufacturing precision is improved, but chip area increases due to additional switches and memory
Solution Approach 1:
The patent eliminates the need for physical trimming components (switches and memory elements) by replacing them with digital correction algorithms. This substitution significantly reduces the chip area required, as digital correction can be implemented using standard ADC logic without requiring additional large-area components
Solution Approach 2:
The patent uses a simplified approach where correction values are generated and applied digitally without requiring physical copies or representations of the trimming network. This avoids the need for duplicate circuitry that would be required in switch-based trimming approaches
3Device complexity
If digital correction is used without physical trimming, then device complexity is reduced, but measurement precision deteriorates when capacitor mismatch becomes too large
Solution Approach 1:
The patent performs preliminary characterization of capacitor mismatch during the conversion process itself. By measuring the actual error introduced by capacitor mismatch and applying correction values based on these measurements, the system ensures high precision without requiring pre-trimming of the capacitors
Solution Approach 2:
The patent implements a feedback mechanism where the converter measures its own conversion results and uses this information to generate correction values. This closed-loop approach ensures that even with large initial capacitor mismatch, the final measurement precision is maintained through real-time error compensation
Data Source
AI summary
Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.