SAR ADC Direct Feedback Loop for Faster Conversion Timing
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Solution Overview
Problem
SAR ADCs with trial decision feedback suffer from low conversion speed due to critical timing paths through latches, limiting their maximum operating frequency.
Innovation Solution
Implementing a direct decision feedback loop that bypasses latches by providing a non-latched feedback signal from the comparator output directly to the DAC, reducing the critical timing path and enhancing conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If trial decision feedback is implemented in SAR ADC, then conversion accuracy is improved, but conversion speed deteriorates due to critical timing paths through latches
Solution Approach 1:
The patent segments the feedback path into two separate paths: a latched path for accuracy and a non-latched direct path for speed. The non-latched feedback signal bypasses the latch circuitry to provide rapid feedback to the DAC, while the latched path maintains accuracy. This segmentation allows the system to achieve both high conversion accuracy and high conversion speed simultaneously.
Solution Approach 2:
The patent introduces a non-latched feedback signal as an intermediary element that mediates between the comparator output and the DAC input. This intermediary path provides a direct, low-latency feedback mechanism that does not depend on latch operation, thereby improving conversion speed without compromising the accuracy provided by the main latched feedback path.
2Stability of the object's composition
If latches are used in the feedback path, then signal stability is improved, but maximum operating frequency deteriorates due to latch delays
Solution Approach 1:
The patent divides the feedback signal into two versions: a latched version for stability and a non-latched version for high-speed operation. The non-latched feedback path eliminates latch delays by providing direct feedback to the DAC, enabling the system to operate at maximum frequencies (e.g., 12GSPS or higher) without being constrained by latch propagation delays.
Solution Approach 2:
The patent prepares the feedback signal in advance by generating a non-latched feedback signal that is ready immediately without waiting for latch operation. This preliminary action ensures that the DAC receives feedback at the earliest possible moment, maximizing the operating frequency while the latched path continues to provide stability when needed.
3Speed
If direct decision feedback loop is implemented, then conversion speed is improved, but timing path complexity increases
Solution Approach 1:
The patent extracts the critical timing path by removing the latch elements from the direct feedback loop. By taking out the latches from this specific path, the patent creates a simplified, low-latency feedback path that directly connects the comparator output to the DAC input, thereby improving conversion speed without introducing significant timing path complexity.
Solution Approach 2:
Instead of using the conventional latched feedback path, the patent inverts the approach by using a non-latched direct feedback path. This inversion eliminates the timing constraints imposed by latch operation, allowing the system to achieve higher conversion speeds while keeping the timing path relatively simple and direct.
Data Source
AI summary
Successive approximation register (SAR) analog-to-digital converters (ADCs) with direct decision feedback loops are disclosed herein. In certain embodiments, a SAR ADC includes a digital-to-analog converter (DAC) that generates an analog output signal, a comparator including an input that receives the analog output signal of the DAC and an output that generates a comparison signal, and an array of switches coupled to the output of the comparator and operable to provide a non-latched feedback signal to a digital input of the DAC.