Parallel SAR ADC Data Path Using Direct Comparator-to-DAC Routing
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Solution Overview
Problem
Traditional successive approximation (SAR) analog-to-digital converters (ADCs) face significant delays in the digital path due to the switched capacitor DAC, comparator, and thermometric encoder, which affect data throughput rates, especially in multiple bit conversions.
Innovation Solution
The implementation of a parallel digital processing path in SAR ADCs, which bypasses the delays introduced by the SAR register and thermometric encoders by directly routing the comparator's output through multiplexers (MUXs) to the switched capacitor DAC, reducing the overall digital data path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional SAR ADC architecture with sequential digital processing is used, then circuit complexity is reduced, but digital path delay increases significantly
Solution Approach 1:
The patent segments the digital processing path into parallel segments: a compressed path for MSBs (bits 3-0) using thermometric encoding, and a direct path for LSBs (bits 7-4) using binary encoding. This segmentation allows different bit groups to be processed simultaneously through separate encoding paths, reducing the overall critical path delay while maintaining manageable circuit complexity in each segment.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing architecture to a multi-dimensional parallel architecture by introducing multiple independent encoding paths (thermometric for MSBs, binary for LSBs) that operate simultaneously. This dimensional change from sequential to parallel processing reduces the critical path delay from approximately 2.8ns to 0.7ns.
2Manufacturing precision
If thermometric encoder is used for all bits, then DNL performance is improved, but processing time and circuit complexity increase
Solution Approach 1:
The patent applies thermometric encoding only to the MSB segment (bits 3-0) where high precision is most critical for establishing the correct voltage range, while using faster binary encoding for the LSB segment (bits 7-4). This segmented approach maintains adequate DNL performance in the critical MSB region while significantly reducing overall processing time.
Solution Approach 2:
Different encoding qualities are applied to different bit segments: high-precision thermometric encoding for MSBs where accuracy is most critical, and standard binary encoding for LSBs where speed is more important. This local quality differentiation optimizes the balance between DNL performance and processing speed.
3Device complexity
If sequential bit-by-bit conversion is used, then circuit simplicity is maintained, but data throughput rate decreases
Solution Approach 1:
The conversion process is segmented into parallel operations: MSB conversion (bits 3-0) and LSB conversion (bits 7-4) occur simultaneously through separate encoding paths. This segmentation enables the ADC to complete multiple bit conversions in parallel, quadrupling the effective data throughput rate while maintaining reasonable circuit complexity through modular design.
Solution Approach 2:
The patent transforms the single-threaded sequential conversion process into a multi-threaded parallel process by introducing independent encoding paths for different bit groups. This dimensional change from sequential to parallel execution dramatically increases productivity while keeping each individual path relatively simple.
Data Source
AI summary
The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.