SAR ADC Dither Correction for Harmonic and Coding Error Control

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Solution Overview

Problem

Capacitor mismatch in analog-to-digital converter arrays leads to the generation of higher-order harmonics, which can degrade spurious free dynamic range (SFDR) and integral/differential non-linearity (INL/DNL), particularly in high-resolution systems.

Innovation Solution

Dynamic dither is added to the capacitor array during intermediate cycles to reduce higher-order harmonics, and the redundancy in the successive-approximation register cycles is used to correct for coding errors, eliminating the need for precise dither subtraction and calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If capacitor arrays are used in successive-approximation register ADCs, then the converter can operate iteratively to generate digital codes representing analog signal levels, but capacitor mismatch leads to generation of higher-order harmonics that degrade spurious free dynamic range and non-linearity

Engineering Contradiction:
Improvespurious free dynamic rangeVSAvoidhigher-order harmonics
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies dither noise to the capacitor array, which intentionally introduces random variations that convert the harmful effect of capacitor mismatch into a beneficial statistical averaging effect. This dithering process transforms deterministic harmonic distortion into random noise that can be filtered more effectively, thereby improving spurious free dynamic range by converting harmful deterministic errors into manageable random variations

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent dynamically changes the operating parameters of the capacitor array by applying dither signals during the conversion process. This parameter change involves modulating the capacitor voltages with controlled noise sequences, which alters the effective transfer characteristics and reduces the impact of fixed mismatch patterns, thereby suppressing higher-order harmonics generation

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If dither is added to the capacitor array to reduce higher-order harmonics, then spurious free dynamic range improves, but coding errors may be introduced that require correction

Engineering Contradiction:
Improvehigher-order harmonicsVSAvoidcoding errors
Core Design Contradiction:
Object-generated harmful factorsVSLoss of information

Solution Approach 1:

The patent employs feedback mechanisms where the output of the successive-approximation register is monitored and used to correct coding errors introduced by dithering. The system continuously adjusts the digital codes based on feedback from the capacitor array response, ensuring that the final output accurately represents the input analog signal despite the intermediate dither-induced variations

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary dithering during intermediate cycles of the conversion process, before the final coding stage. This preliminary action allows the dither to reduce harmonics in early conversion steps while subsequent correction cycles compensate for any coding errors, separating the harmonic reduction function from the final precision coding function

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If precise dither subtraction and calibration are implemented to correct coding errors, then measurement precision improves, but device complexity increases

Engineering Contradiction:
Improvecoding accuracyVSAvoidcalibration requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements self-service calibration where the ADC system performs its own error correction using internal redundancy and feedback mechanisms. The successive-approximation register inherently provides multiple measurement opportunities that allow the system to self-correct coding errors without requiring external calibration equipment or complex external correction circuits, thereby maintaining measurement precision while limiting complexity growth

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10484001B1Multi-bit successive-approximation register analog-to-digital converter
Publication Date: 2019.11.19 TEXAS INSTRUMENTS INC
  • US10484001B1 patent drawing
  • US10484001B1 patent drawing

AI summary

A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.