Multi-Stage SAR ADC Dithering for No-Missing-Code Conversion
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face issues with missing codes due to capacitor mismatches and dynamic errors, which can lead to noise and latency in the conversion process, particularly in applications requiring high resolution and rapid data availability.
Innovation Solution
A multi-stage SAR ADC architecture that includes a first stage for generating most significant bits, a digital-to-analog converter for producing a residue signal, a second stage for generating least significant bits, and dither circuitry to minimize noise and ensure no missing codes, while providing on-the-fly operation by applying dither only to selected bits during conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dither is applied to all bits during conversion, then missing codes are eliminated, but signal-to-noise ratio deteriorates
Solution Approach 1:
The patent applies dither selectively only to specific bits (MSBs or LSBs) rather than all bits during conversion. This localized application eliminates missing codes in the affected bit positions while minimizing noise impact on the overall signal, thereby resolving the contradiction between reliability and signal quality.
2Quantity of substance
If multi-stage architecture is used, then capacitor size is reduced, but device complexity increases
Solution Approach 1:
The patent divides the ADC conversion process into multiple stages, with each stage handling a subset of bits. This segmentation allows the use of smaller capacitors in each stage compared to a single-stage design, while the modular structure manages complexity through systematic organization of the conversion steps.
3Productivity
If dither is applied during conversion, then calibration is eliminated, but noise increases
Solution Approach 1:
The patent changes the parameter of dither application from continuous (all bits) to selective (specific bits only). This parameter modification enables the system to achieve calibration-free operation with acceptable noise levels, improving conversion speed while controlling noise impact through selective dither placement.
Data Source
AI summary
A multi-stage analog-to-digital converter includes a signal input terminal, a first stage analog-to-digital converter, a digital-to-analog converter; a second stage analog-to-digital converter, and dither circuitry. The first stage analog-to-digital converter includes an input coupled to the signal input terminal. The digital-to-analog converter includes an input coupled to an output of the first stage analog-to-digital converter, and an input coupled to the signal input terminal. The second stage analog-to-digital converter includes a first input coupled to an output of the digital-to-analog converter. The dither circuitry is coupled to a second input of the second stage analog-to-digital converter, and is configured to provide a dither signal to the second stage analog-to-digital converter during selection of fewer than all bits of a digital value of a residue signal received from the digital-to-analog converter.