SAR ADC Driver Calibration for Faster, Stable TDC Conversion
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) in time-to-digital converters (TDCs) face limitations due to settling time and parasitic capacitance, leading to ADC clipping and conversion time issues exacerbated by process, voltage, and temperature variations.
Innovation Solution
The implementation of an ADC-assisted TDC system with a programmable ADC driver that calibrates the amplitude and common-mode of input signals, using TDC buffers and a programmable ADC driver to optimize input signals, reduce ADC clipping, and minimize conversion time through one-time and online calibration processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SAR ADC is used in TDC to improve resolution, then measurement precision is improved, but settling time increases due to parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by performing calibration of the ADC driver's common-mode voltage and gain parameters before actual TDC measurements. The calibration process pre-determines optimal operating parameters for the ADC driver, ensuring that during subsequent measurement operations, the ADC operates at peak performance with minimized settling time. The calibration stores optimal control values that are reused during normal operation, avoiding the need for repeated calibration while maintaining optimal settling characteristics.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the common-mode voltage and gain parameters of the ADC driver based on calibration results. The calibration process varies these parameters to find optimal values that minimize settling time while maintaining measurement accuracy. During operation, these calibrated parameters are applied to optimize the ADC's response time and reduce the impact of parasitic capacitance on settling time.
2Manufacturing precision
If ADC driver is added to optimize input signal, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the ADC driver calibration functionality directly into the existing TDC architecture. The calibration circuitry and control logic are combined with the ADC and TDC components, sharing common resources such as control signals, power supply, and signal paths. This integration approach enables precise control of the ADC driver's common-mode and gain parameters without adding significant external components or increasing overall system complexity.
Solution Approach 2:
The patent implements self-service through automated calibration processes that perform their own optimization without requiring external intervention. The calibration circuit automatically adjusts the ADC driver parameters by measuring its own performance characteristics and applying corrective control signals. This self-calibrating capability eliminates the need for complex external calibration equipment or manual adjustment mechanisms, thereby improving manufacturing precision while keeping device complexity manageable.
Data Source
AI summary
An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.