SAR ADC Dual-DAC Sampling for Higher Speed in Compact Circuits
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Solution Overview
Problem
Existing successive approximation AD converters face a challenge in enhancing speed without increasing circuit size, particularly when using the time-interleaved method with multiple SARADCs, and when using a single SARADC, speed enhancement is not achievable.
Innovation Solution
The AD converter employs two DACs connected in parallel, with a comparison unit and additional components like sample-and-hold switches and single-ended to differential conversion circuits, allowing parallel sampling and conversion without significantly increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the time-interleaved method with multiple SARADCs is used to enhance speed, then the AD conversion speed is improved, but the circuit size increases
Solution Approach 1:
The patent divides the AD conversion process into two separate phases: a sampling period for signal acquisition and an AD conversion period for digital conversion. This temporal segmentation allows the single SARADC to operate efficiently without requiring multiple parallel converters, thus maintaining compact circuit size while achieving high-speed conversion through optimized timing sequences.
Solution Approach 2:
The patent implements dynamic switching between sampling and conversion modes using control signals that coordinate the operation of sample-and-hold circuits, switches, and the SARADC. This dynamic time-division multiplexing enables the system to adapt its operational state based on whether sampling or conversion is currently required, maximizing resource utilization without increasing hardware complexity.
2Area of stationary object
If a single SARADC is used to reduce circuit size, then the circuit size is reduced, but the AD conversion speed cannot be enhanced
Solution Approach 1:
The patent performs preliminary sampling and signal conditioning during the sampling period using sample-and-hold circuits and switching networks. By preparing the input signal in advance during the sampling phase, the SARADC can immediately begin high-speed conversion during the conversion period without waiting for signal conditioning, thus achieving enhanced overall conversion speed with a single converter.
Solution Approach 2:
The patent ensures continuous operation by overlapping the sampling period of one channel with the conversion period of another, or by rapidly alternating between sampling and conversion modes. This continuous utilization of the SARADC and associated circuits eliminates idle time and maintains high conversion throughput without requiring multiple parallel converters.
3Productivity
If multiple SARADCs are used for time-interleaved conversion, then the conversion speed is improved, but the number of components and circuit complexity increase
Solution Approach 1:
The patent designs the SARADC and associated circuits to perform multiple functions: the same SARADC conducts both sampling and AD conversion, the same switching network routes signals for both sampling and conversion phases, and the same reference voltage generator serves both operational modes. This multi-functionality eliminates the need for separate dedicated circuits for each function, reducing overall component count while maintaining high conversion throughput.
Data Source
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AI summary
The present technology is intended to enhance the speed of a successive approximation AD converter while suppressing an increase in circuit size. An analog to digital (AD) converter includes a first digital-to-analog converter (DAC), a second DAC, and a comparison unit. Furthermore, the first DAC has a capacitor that holds a first input signal during a first sampling period. Furthermore, the second DAC has a capacitor that holds a second input signal during a second sampling period. Furthermore, the comparison unit is connected to the first and second DACs.