SAR ADC Clock Duty Cycle Control for Complete Bit Conversion
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Solution Overview
Problem
Determining the correct duty cycle for the sampling clock in Successive Approximation Register Analogue to Digital Converters (SAR ADCs) is challenging, as it involves a trade-off between completing conversion quickly and ensuring enough time for bit conversion, with bit loss affecting performance significantly.
Innovation Solution
A dynamic duty cycle is implemented for the clock domain, where the duty cycle of the clock clocking the analogue to digital converter is controlled by a feedback signal indicating completion of sample conversion, allowing for flexible adjustment to balance conversion and sampling times, ensuring all bits are converted without loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the SAR ADC finishes the sample conversion quickly, then the conversion time is reduced, but the surplus time is spent doing nothing before the sampling phase begins
Solution Approach 1:
The patent applies dynamics by making the clock duty cycle adjustable rather than fixed. The duty cycle of the sampling clock can be dynamically modified based on the actual conversion speed of the SAR ADC, allowing the system to adapt the clocking parameters to match the converter's performance characteristics and eliminate wasted time.
Solution Approach 2:
The patent changes the parameter of clock duty cycle to optimize the timing. By adjusting the duty cycle parameter of the sampling clock, the system can synchronize the clock periods with the actual conversion duration, ensuring that the sampling phase begins precisely when conversion completes, thereby eliminating surplus idle time.
2Speed
If the SAR ADC is too slow, then conversion takes longer, but there may not be enough time in the conversion phase to convert all the bits
Solution Approach 1:
The patent applies dynamics by enabling dynamic adjustment of the clock duty cycle based on the ADC's actual conversion speed. This allows the system to adaptively extend or reduce the conversion phase duration to ensure complete bit conversion, preventing data loss while accommodating variations in conversion speed due to ageing, parasitic capacitances, or supply voltage variations.
Solution Approach 2:
The patent implements feedback by monitoring the conversion completion status and using this information to adjust the clock duty cycle. The system observes whether all bits are successfully converted and modifies the timing parameters accordingly, ensuring that slower ADCs receive extended conversion time while faster ADCs operate with optimized, shorter periods.
3Device complexity
If a fixed duty cycle is used for the sampling clock, then the design is simpler, but it cannot adapt to variations in ADC speed due to ageing, parasitic capacitances, or supply voltage
Solution Approach 1:
The patent transitions from a static fixed duty cycle to a dynamic adjustable duty cycle system. The sampling clock's duty cycle can be modified in response to ADC performance variations, enabling the system to adapt to ageing effects, parasitic capacitance changes, and supply voltage variations while maintaining reliable operation.
Solution Approach 2:
The patent changes the duty cycle parameter of the sampling clock from a fixed value to a variable parameter that can be adjusted based on ADC performance. This parameter change enables the system to optimize timing for different operating conditions and ADC speed variations without requiring complete redesign of the clocking architecture.
Data Source
AI summary
A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.